C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 68
C8051F930DK
Manufacturer Part Number
C8051F930DK
Description
KIT DEV C8051F920,F921,F930,F931
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930DK
Contents
Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F920, F921, F930, F931
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F930DK
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F93x-C8051F92x
5.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. The minimum tracking time is given in Table 4.9. The AD0TM bit in register ADC0CN controls
the ADC0 track-and-hold mode. In its default state when Burst Mode is disabled, the ADC0 input is contin-
uously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in
low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR
clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in
low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of
CNVSTR (see Figure 5.2). Tracking can also be disabled (shutdown) when the device is in low power
standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are fre-
quently changed, due to the settling time requirements described in “5.2.4. Settling Time Requirements” on
page 70.
68
(AD0CM[2:0]=000, 001,010
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0)
Timer 1, Timer 3 Overflow
Write '1' to AD0BUSY,
(AD0CM[2:0]=100)
Timer 0, Timer 2,
SAR Clocks
AD0TM=1
AD0TM=0
011, 101)
AD0TM=1
AD0TM=0
CNVSTR
Clocks
Clocks
SAR
SAR
Low Power
or Convert
Low Power
or Convert
Track or
A. ADC0 Timing for External Trigger Source
Convert
Track or Convert
B. ADC0 Timing for Internal Trigger Source
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Track
Track
Rev. 1.1
1 2 3 4 5 6 7 8 9
Convert
Convert
Convert
Convert
10 11 12 13 14
Low Power Mode
Track
Low Power
Mode
Track
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