C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 10

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

C8051F93x-C8051F92x
6. Programmable Current Reference (IREF0)
7. Comparators
8. CIP-51 Microcontroller
9. Memory Organization
10. External Data Memory Interface and On-Chip XRAM
11. Special Function Registers
12. Interrupt Handler
13. Flash Memory
14. Power Management
15. Cyclic Redundancy Check Unit (CRC0)
16. On-Chip DC-DC Converter (DC0)
17. Voltage Regulator (VREG0)
18. Reset Sources
19. Clocking Sources
20. SmaRTClock (Real Time Clock)
21. Port Input/Output
10
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (V
Figure 5.10. Voltage Reference Functional Block Diagram...................................... 86
Figure 7.1. Comparator 0 Functional Block Diagram ............................................... 90
Figure 7.2. Comparator 1 Functional Block Diagram ............................................... 91
Figure 7.3. Comparator Hysteresis Plot ................................................................... 92
Figure 7.4. CPn Multiplexer Block Diagram.............................................................. 97
Figure 8.1. CIP-51 Block Diagram.......................................................................... 100
Figure 9.1. C8051F93x-C8051F92x Memory Map ................................................. 109
Figure 9.2. Flash Program Memory Map................................................................ 110
Figure 10.1. Multiplexed Configuration Example.................................................... 115
Figure 10.2. Multiplexed to Non-Multiplexed Configuration Example..................... 116
Figure 10.3. EMIF Operating Modes ...................................................................... 117
Figure 10.4. Multiplexed 16-bit MOVX Timing........................................................ 122
Figure 10.5. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 123
Figure 10.6. Multiplexed 8-bit MOVX with Bank Select Timing .............................. 124
Figure 13.1. Flash Program Memory Map.............................................................. 147
Figure 14.1. C8051F93x-C8051F92x Power Distribution....................................... 157
Figure 15.1. CRC0 Block Diagram ......................................................................... 164
Figure 15.2. Bit Reverse Register .......................................................................... 170
Figure 16.1. DC-DC Converter Block Diagram....................................................... 171
Figure 16.2. DC-DC Converter Configuration Options ........................................... 174
Figure 18.1. Reset Sources.................................................................................... 180
Figure 18.2. Power-Fail Reset Timing Diagram ..................................................... 181
Figure 18.3. Power-Fail Reset Timing Diagram ..................................................... 182
Figure 19.1. Clocking Sources Block Diagram ....................................................... 187
Figure 19.2. 25 MHz External Crystal Example...................................................... 189
Figure 20.1. SmaRTClock Block Diagram.............................................................. 196
Figure 20.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results.......... 204
Figure 21.1. Port I/O Functional Block Diagram ..................................................... 212
Rev. 0.2
REF
= 1.68 V) ..... 84