C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 126

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

C8051F93x-C8051F92x
11. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F93x-C8051F92x's resources and
peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well
as implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F93x-C8051F92x. This allows the addition of new functionality while retaining compatibility with the
MCS-51™ instruction set. Table 11.1 and Table 11.2 list the SFRs implemented in the C8051F93x-
C8051F92x device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 11.3, for a detailed description of each register.
126
F8 SPI0CN
F0
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3
E0
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3
D0
C8 TMR2CN REG0CN
C0 SMB0CN SMB0CF
B8
B0 SPI1CN
A8
A0
98 SCON0
90
88
80
(bit addressable)
TCON
PSW
ACC
0(8)
P2
P1
P0
IP
IE
B
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0)
IREF0CN
OSCXCN
SPI0CFG
TMR3CN
REF0CN PCA0CPL5 PCA0CPH5
CLKSEL
P0MDIN
SBUF0
PCA0L
TMOD
XBR0
1(9)
SP
SMB0DAT ADC0GTL ADC0GTH
TMR2RLL TMR2RLH
TMR3RLL TMR3RLH
SPI0CKR
ADC0AC
CPT1CN
P1MDIN
OSCICN
EMI0CN
PCA0H
XBR1
DPL
2(A)
TL0
PCA0CPL0 PCA0CPH0 PCA0CPL4
ADC0MX
SPI0DAT
CPT0CN
P2MDIN
OSCICL
EMI0CF
XBR2
DPH
3(B)
TL1
Rev. 1.1
SMB0ADR
P0MDOUT
RTC0ADR
SPI1CFG
CPT1MD
ADC0CF
P0SKIP
IT01CF
TMR2L
TMR3L
TH0
4(C)
SMB0ADM
P1MDOUT
RTC0DAT
ADC0LTL
SPI1CKR
PMU0CF
CPT0MD
P1SKIP
TMR2H
TMR3H
ADC0L
TH1
5(D)
PCA0CPM4 PCA0PWM
PCA0CPM5
PCA0CPH4
PCA0CPH3
P2MDOUT
RTC0KEY
ADC0LTH
CPT1MX
SPI1DAT
CKCON
P2SKIP
ADC0H
DC0CF
FLSCL
EIP1
EIE1
6(E)
SFRPAGE
VDM0CN
RSTSRC
P0MASK
P1MASK
CPT0MX
EMI0TC
DC0CN
P0MAT
P1MAT
PSCTL
FLKEY
PCON
EIP2
EIE2
7(F)