C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 290

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

C8051F93x-C8051F92x
25.2.3. Comparator 0/SmaRTClock Capture Mode
The Capture Mode in Timer 2 allows either Comparator 0 or the SmaRTClock period to be measured
against the system clock or the system clock divided by 12. Comparator 0 and the SmaRTClock period can
also be compared against each other. Timer 2 Capture Mode is enabled by setting TF2CEN to 1. Timer 2
should be in 16-bit auto-reload mode when using Capture Mode.
When Capture Mode is enabled, a capture event will be generated either every Comparator 0 rising edge
or every 8 SmaRTClock clock cycles, depending on the T2XCLK1 setting. When the capture event occurs,
the
(TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 interrupts are enabled).
By recording the difference between two successive timer capture values, the Comparator 0 or SmaRT-
Clock period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster
than the capture clock to achieve an accurate reading.
For example, if T2ML = 1b, T2XCLK1 = 0b, and TF2CEN = 1b, Timer 2 will clock every SYSCLK and cap-
ture every SmaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two
successive captures is 5984, then the SmaRTClock clock is:
24.5 MHz/(5984/8) = 0.032754 MHz or 32.754 kHz.
This mode allows software to determine the exact SmaRTClock frequency in self-oscillate mode and the
time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the
capacitance of a Touch Sense Switch.
290
SmaRTClock / 8
SmaRTClock / 8
contents
Comparator 0
SYSCLK / 12
Comparator 0
SYSCLK
of
T2XCLK[1:0]
T2XCLK1
Timer
X0
01
11
0
1
Figure 25.6. Timer 2 Capture Mode Block Diagram
M
T
H
3
2
M
T
3
L
CKCON
M
T
H
2
(TMR2H:TMR2L)
M
T
0
1
2
L
M
T
1
M
T
0
S
C
A
1
TF2CEN
S
C
A
0
TR2
Rev. 1.1
Capture
are
TCLK
loaded
TMR2RLL TMR2RLH
TMR2L
into
TMR2H
the
Timer 2
T2XCLK1
T2XCLK0
TF2CEN
T2SPLIT
TF2LEN
TF2H
TF2L
TR2
reload
registers
Interrupt