C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 181

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

18.1. Power-On (VBAT Supply Monitor) Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
V
Figure 18.3 plots the power-on and V
power-on reset delay (T
3.6 V).
Note: The maximum V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
POR
BAT
See specification
table for min/max
voltages.
. An additional delay occurs before the device is released from reset; the delay decreases as the
ramp time increases (V
before V
BAT
Logic HIGH
Logic LOW
reaches the V
~0.8
~0.5
0.6
DD
Figure 18.2. Power-Fail Reset Timing Diagram
PORDelay
ramp time is 3 ms; slower ramp times may cause the device to be released from reset
RST
POR
BAT
) is typically 3 ms (V
level.
V
ramp time is defined as how fast V
POR
DD
monitor reset timing. For valid ramp times (less than 3 ms), the
Power-On
Reset
Rev. 1.1
T
PORDelay
BAT
C8051F93x-C8051F92x
= 0.9 V), 7 ms (V
Power-On
BAT
Reset
BAT
ramps from 0 V to V
= 1.8 V), or 15 ms (V
T
PORDelay
BAT
settles above
VBAT
BAT
POR
t
181
).
=