C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 121

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

SFR Definition 10.3. EMI0TC: External Memory Timing Control
SFR Page = 0x0; SFR Address = 0xAF
Reset
Name
Type
Bit
7:4
3:2
1:0
Bit
Name
EAS
EWR
R/W
EAH
7
1
EAS[1:0]
Address Setup Time Select Bits.
Controls the timing parameter T
00: Address Setup Time = 0 SYSCLK cycles.
01: Address Setup Time = 1 SYSCLK cycles.
10: Address Setup Time = 2 SYSCLK cycles.
11: Address Setup Time = 3 SYSCLK cycles.
RD and WR Pulse Width Select.
Controls the timing parameter T
0000: WR and RD pulse width = 1 SYSCLK cycle.
0001: WR and RD pulse width = 2 SYSCLK cycles.
0010: WR and RD pulse width = 3 SYSCLK cycles.
0011: WR and RD pulse width = 4 SYSCLK cycles.
0100: WR and RD pulse width = 5 SYSCLK cycles.
0101: WR and RD pulse width = 6 SYSCLK cycles.
0110: WR and RD pulse width = 7 SYSCLK cycles.
0111: WR and RD pulse width = 8 SYSCLK cycles.
1000: WR and RD pulse width = 9 SYSCLK cycles.
1001: WR and RD pulse width = 10 SYSCLK cycles.
1010: WR and RD pulse width = 11 SYSCLK cycles.
1011: WR and RD pulse width = 12 SYSCLK cycles.
1100: WR and RD pulse width = 13 SYSCLK cycles.
1101: WR and RD pulse width = 14 SYSCLK cycles.
1110: WR and RD pulse width = 15 SYSCLK cycles.
1111: WR and RD pulse width = 16 SYSCLK cycles.
Address Hold Time Select Bits.
Controls the timing parameter T
00: Address Hold Time = 0 SYSCLK cycles.
01: Address Hold Time = 1 SYSCLK cycles.
10: Address Hold Time = 2 SYSCLK cycles.
11: Address Hold Time = 3 SYSCLK cycles.
R/W
1
6
R/W
5
1
R/W
Rev. 1.1
4
1
EWR[3:0]
ACS
ACW
ACH
.
.
.
C8051F93x-C8051F92x
Function
R/W
3
1
R/W
2
1
R/W
1
1
EAH[1:0]
R/W
0
1
121