C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 220

KIT DEV C8051F920,F921,F930,F931

C8051F930DK

Manufacturer Part Number
C8051F930DK
Description
KIT DEV C8051F920,F921,F930,F931
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F930DK

Contents
Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F920, F921, F930, F931
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1473

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F930DK
Manufacturer:
Silicon Labs
Quantity:
135
C8051F93x-C8051F92x
SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1
SFR Page = 0x0; SFR Address = 0xE2
220
Note: SPI1 can be assigned either 3 or 4 Port I/O pins.
Reset
Name
Type
2:0
Bit
Bit
7
6
5
4
3
PCA0ME PCA0 Module I/O Enable.
Unused
SPI1E
Name
ECIE
R/W
T1E
T0E
7
0
Unused.
Read = 0b; Write = Don’t Care.
SPI1 I/O Enable.
0: SPI0 I/O unavailable at Port pin.
1: SCK (for SPI1) routed to P1.0.
Timer1 Input Enable.
0: T1 input unavailable at Port pin.
1: T1 input routed to Port pin.
Timer0 Input Enable.
0: T0 input unavailable at Port pin.
1: T0 input routed to Port pin.
PCA0 External Counter Input (ECI) Enable.
0: PCA0 external counter input unavailable at Port pin.
1: PCA0 external counter input routed to Port pin.
000: All PCA0 I/O unavailable at Port pin.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2 CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.
111: Reserved.
SPI1E
MISO (for SPI1) routed to P1.1.
MOSI (for SPI1) routed to P1.2.
NSS (for SPI1) routed to P1.3 only if SPI1 is configured to 4-wire mode.
R/W
0
6
R/W
T1E
5
0
T0E
R/W
Rev. 1.1
4
0
Function
ECIE
R/W
3
0
R/W
2
0
PCA0ME[2:0]
R/W
1
0
R/W
0
0

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