C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 162
C8051F930DK
Manufacturer Part Number
C8051F930DK
Description
KIT DEV C8051F920,F921,F930,F931
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930DK
Contents
Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F920, F921, F930, F931
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F930DK
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F93x-C8051F92x
SFR Definition 14.1. PMU0CF: Power Management Unit Configuration
SFR Page = 0x0; SFR Address = 0xB5
162
Notes:
Reset
Name
Bit
Type
7
6
5
4
3
2
1
0
Bit
1. Read-modify-write operations (ORL, ANL, etc.) should not be used on this register. Wake-up sources must
2. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in Suspend or Sleep
be re-enabled each time the SLEEP or SUSPEND bits are written to 1.
Mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from suspend or sleep modes.
SUSPEND
RTCFWK
RTCAWK
PMATWK
CPT0WK
RSTWK
CLEAR
SLEEP
SLEEP
Name
W
7
0
SUSPEND
Sleep Mode Select
Suspend Mode Select
Wake-up Flag Clear
Reset Pin Wake-up Flag
SmaRTClock Oscillator
Fail Wake-up Source
Enable and Flag
SmaRTClock Alarm
Wake-up Source Enable
and Flag
Port Match Wake-up
Source Enable and Flag
Comparator0 Wake-up
Source Enable and Flag
W
6
0
Description
CLEAR
W
5
0
RSTWK
Varies
Rev. 1.1
Writing 1 places the
device in Sleep Mode.
Writing 1 places the
device in Suspend Mode.
Writing 1 clears all wake-
up flags.
N/A
0: Disable wake-up on
SmaRTClock Osc. Fail.
1: Enable wake-up on
SmaRTClock Osc. Fail.
0: Disable wake-up on
SmaRTClock Alarm.
1: Enable wake-up on
SmaRTClock Alarm.
0: Disable wake-up on
Port Match Event.
1: Enable wake-up on
Port Match Event.
0: Disable wake-up on
Comparator0 rising edge.
1: Enable wake-up on
Comparator0 rising edge.
R
4
RTCFWK
Varies
Write
R/W
3
RTCAWK
Varies
R/W
2
N/A
N/A
N/A
Set to 1 if a glitch has
been detected on RST.
Set to 1 if the SmaRT-
Clock Oscillator has failed.
Set to 1 if a SmaRTClock
Alarm has occurred.
Set to 1 if a Port Match
Event has occurred.
Set to 1 if Comparator0
rising edge caused the last
reset.
PMATWK
Varies
R/W
1
Read
1,2
CPT0WK
Varies
R/W
0
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