AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 749

KIT EVAL FOR AT91SAMG45/9M10

AT91SAM9M10-G45-EK

Manufacturer Part Number
AT91SAM9M10-G45-EK
Description
KIT EVAL FOR AT91SAMG45/9M10
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets

Specifications of AT91SAM9M10-G45-EK

Contents
Board, Cables, Power Supply
Processor To Be Evaluated
AT91SAM9M10
Processor Series
AT91SAM9
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, JTAG
Operating Supply Voltage
5 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Features
Two High Speed USB Hosts, LCD TFT Display
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9M10,
Rohs Compliant
Yes
For Use With/related Products
AT91SAM9M10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9M10-G45-EK
Manufacturer:
INFINEON
Quantity:
10 000
Part Number:
AT91SAM9M10-G45-EK
Manufacturer:
Atmel
Quantity:
135
AT91SAM9M10
0 = The HSMCI is not ready for new data transfer. Cleared at the end of the card response.
1 = The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a
free internal data receive buffer of the card.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
For all the read operations, the NOTBUSY flag is cleared at the end of the host command.
For the Infinite Read Multiple Blocks, the NOTBUSY flag is set at the end of the STOP_TRANSMISSION host command
(CMD12).
For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block.
For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data
block.
• SDIOIRQA: SDIO Interrupt for Slot A
0 = No interrupt detected on SDIO Slot A.
1 = An SDIO Interrupt on Slot A occurred. Cleared when reading the HSMCI_SR.
• SDIOWAIT: SDIO Read Wait Operation Status
0 = Normal Bus operation.
1 = The data bus has entered IO wait state.
• CSRCV: CE-ATA Completion Signal Received
0 = No completion signal received since last status read operation.
1 = The device has issued a command completion signal on the command line. Cleared by reading in the HSMCI_SR
register.
• RINDE: Response Index Error
0 = No error.
1 = A mismatch is detected between the command index sent and the response index received. Cleared when writing in
the HSMCI_CMDR.
• RDIRE: Response Direction Error
0 = No error.
1 = The direction bit from card to host in the response has not been detected.
• RCRCE: Response CRC Error
0 = No error.
1 = A CRC7 error has been detected in the response. Cleared when writing in the HSMCI_CMDR.
• RENDE: Response End Bit Error
0 = No error.
1 = The end bit of the response has not been detected. Cleared when writing in the HSMCI_CMDR.
• RTOE: Response Time-out Error
0 = No error.
1 = The response time-out set by MAXLAT in the HSMCI_CMDR has been exceeded. Cleared when writing in the
HSMCI_CMDR.
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6355B–ATARM–21-Jun-10

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