AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 261
AT91SAM9M10-G45-EK
Manufacturer Part Number
AT91SAM9M10-G45-EK
Description
KIT EVAL FOR AT91SAMG45/9M10
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Specifications of AT91SAM9M10-G45-EK
Contents
Board, Cables, Power Supply
Processor To Be Evaluated
AT91SAM9M10
Processor Series
AT91SAM9
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, JTAG
Operating Supply Voltage
5 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Features
Two High Speed USB Hosts, LCD TFT Display
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9M10,
Rohs Compliant
Yes
For Use With/related Products
AT91SAM9M10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-G45-EK
Manufacturer:
INFINEON
Quantity:
10 000
Company:
Part Number:
AT91SAM9M10-G45-EK
Manufacturer:
Atmel
Quantity:
135
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22.7.2
Name:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• COUNT: DDRSDRC Refresh Timer Count
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh
sequence is initiated.
SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the DDRSDRC clock fre-
quency (MCK: Master Clock) and the number of rows in the device.
For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of Refresh Timer Count bit is pro-
grammed: (((64 x 10
6355B–ATARM–21-Jun-10
31
23
15
–
–
–
7
DDRSDRC Refresh Timer Register
-3
)/8192) x100 x10
30
22
14
DDRSDRC_RTR
Read-write
See
–
–
–
6
Table 22-9
29
21
13
–
–
–
5
6
= 781 or 0x030D.
28
20
12
–
–
–
4
COUNT
“DDRSDRC Write Protect Mode Register” on page
27
19
11
–
–
3
26
18
10
–
–
2
COUNT
AT91SAM9M10
25
17
–
–
9
1
275.
24
16
–
–
8
0
261
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