AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 343

• Manufacturer Part Number: AT91SAM9M10-G45-EK
• Description: KIT EVAL FOR AT91SAMG45/9M10
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9M10-G45-EK

• Contents: Board, Cables, Power Supply
• Processor To Be Evaluated: AT91SAM9M10
• Processor Series: AT91SAM9
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, JTAG
• Operating Supply Voltage: 5 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Features: Two High Speed USB Hosts, LCD TFT Display
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9M10,
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9M10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.2.1
26.2.1.1
26.2.1.2
6355B–ATARM–21-Jun-10
Main Application Modes
Normal Mode
USB HS and LP-DDR Mode
Figure 26-1. AT91SAM9M10 Power Management Controller Block Diagram
The Power Management Controller provides 3 main application modes.
• PLLA and UPLL are running respectively at 400 MHz and 480 MHz
• USB Device High Speed and Host EHCI High Speed operations are allowed
• Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
• System Input clock is PLLACK, PCK is 400 MHz
• MDIV is ‘11’, MCK is 133 MHz
• DDR2 can be used at up to 133 MHz
• Only UPLL is running at 480 MHz, PLLA power consumption is saved
• USB Device High Speed and Host EHCI High Speed operations are allowed
• Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
• System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz
• MDIV is ‘01’, MCK is 120 MHz
• Only LP-DDR can be used at up to 120 MHz
PLLACK
/1,/2
UPLLCK
MAINCK
SLCK
USBS
Master Clock Controller
/1,/2,/4,.../64
Prescaler
UPLLCK
MAINCK
USBDIV+1
SLCK
Programmable Clock Controller
/1 /2
X /1 /1.5 /2
/4
Divider
/1,/2,/4,...,/64
/3 /4
Prescaler
UHP48M
UHP12M
ON/OFF
OHCI
EHCI
USB
USB
Clock Controller
Processor
Controller
Clock
Peripherals
ON/OFF
AT91SAM9M10
pck[..]
MCK
periph_clk[..]
SysClk DDR
PCK
int
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