AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 342

• Manufacturer Part Number: AT91SAM9M10-G45-EK
• Description: KIT EVAL FOR AT91SAMG45/9M10
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9M10-G45-EK

• Contents: Board, Cables, Power Supply
• Processor To Be Evaluated: AT91SAM9M10
• Processor Series: AT91SAM9
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, JTAG
• Operating Supply Voltage: 5 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Features: Two High Speed USB Hosts, LCD TFT Display
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9M10,
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9M10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26. Power Management Controller (PMC)
26.1
26.2
342
Description
Embedded Characteristics
AT91SAM9M10
The Power Management Controller (PMC) optimizes power consumption by controlling all sys-
tem and user peripheral clocks. The PMC enables/disables the clock inputs to many of the
peripherals and the ARM Processor.
The Power Management Controller provides all the clock signals to the system.
PMC input clocks:
PMC output clocks
Note:
This allows the software control of five flexible operating modes:
• UPLLCK: From UTMI PLL
• PLLACK From PLLA
• SLCK: slow clock from OSC32K or internal RC OSC
• MAINCK: from 12 MHz external oscillator
• Processor Clock PCK
• Master Clock MCK, in particular to the Matrix and the memory interfaces. The divider can be
• DDR system clock equal to 2xMCK
• USB Host EHCI High speed clock (UPLLCK)
• USB OHCI clocks (UHP48M and UHP12M)
• Independent peripheral clocks, typically at the frequency of MCK
• Two programmable clock outputs: PCK0 and PCK1
• Normal Mode, processor and peripherals running at a programmable frequency
• Idle Mode, processor stopped waiting for an interrupt
• Slow Clock Mode, processor and peripherals running at low frequency
• Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor
• Backup Mode, Main Power Supplies off, VDDBU powered by a battery
1,2,3 or 4
stopped waiting for an interrupt
DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK).
6355B–ATARM–21-Jun-10