AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 489

KIT EVAL FOR AT91SAMG45/9M10

AT91SAM9M10-G45-EK

Manufacturer Part Number
AT91SAM9M10-G45-EK
Description
KIT EVAL FOR AT91SAMG45/9M10
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets

Specifications of AT91SAM9M10-G45-EK

Contents
Board, Cables, Power Supply
Processor To Be Evaluated
AT91SAM9M10
Processor Series
AT91SAM9
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, JTAG
Operating Supply Voltage
5 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Kit Contents
Board
Features
Two High Speed USB Hosts, LCD TFT Display
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
AT91SAM9M10,
Rohs Compliant
Yes
For Use With/related Products
AT91SAM9M10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9M10-G45-EK
Manufacturer:
INFINEON
Quantity:
10 000
Part Number:
AT91SAM9M10-G45-EK
Manufacturer:
Atmel
Quantity:
135
Figure 31-6. Master Write with One Data Byte
Figure 31-7. Master Write with Multiple Data Bytes
489
TXCOMP
TXRDY
TWCK
TWD
AT91SAM9M10
Write THR (Data n)
S
DADR
After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is
written in the TWI_THR or until a STOP command is performed.
See
TXCOMP
TXRDY
W
Figure
TWD
Write THR (DATA)
A
31-6,
S
STOP Command sent (write in TWI_CR)
DATA n
Figure
DADR
31-7, and
A
W
Figure
Write THR (Data n+1)
A
31-8.
DATA
DATA n+1
STOP command performed
(by writing in the TWI_CR)
A
Write THR (Data n+2)
Last data sent
P
A
DATA n+2
6355B–ATARM–21-Jun-10
A
P

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