MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 91

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6.19
5.6.19.1
This read-only bit reflects the state of the interrupt to the 56800E core.
5.6.19.2
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being
sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service
routine.
Note:
5.6.19.3
This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken.
In the case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated
when the 56800E core jumps to a new interrupt service routine.
Freescale Semiconductor
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$Base + $16
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
RESET
Write
Read
Interrupt Control Register (ICTRL)
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
Interrupt (INT)—Bit 15
Interrupt Priority Level (IPIC)—Bits 14–13
Vector Number - Vector Address Bus (VAB)—Bits 12–6
INT
15
0
IPIC_VALUE[1:0]
14
0
Figure 5-21 Interrupt Control Register (ICTRL)
IPIC
00
01
10
11
13
0
Table 5-4 Interrupt Priority Encoding
12
0
56F8037/56F8027 Data Sheet, Rev. 7
11
0
No interrupt or SWILP
Current Interrupt
Priority Level
Priority 2 or 3
10
0
Priority 0
Priority 1
VAB
9
0
8
0
7
0
Exception Priority
Priorities 0, 1, 2, 3
Required Nested
Priorities 1, 2, 3
6
0
Priorities 2, 3
Priority 3
INT_
DIS
5
0
4
1
1
3
1
1
2
1
1
Register Descriptions
1
0
0
0
0
0
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