MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 44

BOARD EVAL FOR MC56F8037

MC56F8037EVM

Manufacturer Part Number
MC56F8037EVM
Description
BOARD EVAL FOR MC56F8037
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of MC56F8037EVM

Contents
Board, Cables, CD, Debugger
Silicon Manufacturer
Freescale
Core Architecture
56800/E
Core Sub-architecture
56800/E
Silicon Core Number
MC56F
Silicon Family Name
MC56F80xx
Kit Contents
MC56F8037EVM, USB-JTAG Adapter, Cables, CD
Rohs Compliant
Yes
For Use With/related Products
MC56F8037
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
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3.8 Alternate External Clock Input
The recommended method of connecting an external clock is illustrated in
source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary).
The user has the option of using GPIO6/RXD/CLKIN or GPIOB5/TA1/FAULT3/CLKIN as external
clock input.
Part 4 Memory Maps
4.1 Introduction
The 56F8037/56F8027 device is a 16-bit motor-control chip based on the 56800E core. It uses a
Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is
shared by both spaces and Flash memory is used only in Program space.
This section provides memory maps for:
On-chip memory sizes for the device are summarized in
identified in the “Use Restrictions” column of
44
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
Figure 3-3 Connecting an External Clock Signal using XTAL
Figure 3-4 Connecting an External Clock Signal using GPIO
CLKMODE = 1
56F8037/56F8027 Data Sheet, Rev. 7
56F8037/56F8027
External Clock
Table
GPIO
External
XTAL
Clock
56F8037/56F8027
4-1.
Table
GND or
EXTAL
GPIO
4-1. Flash memories’ restrictions are
Figure
3-3. The external clock
Freescale Semiconductor

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