MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 123

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.22.4
This field selects the alternate input source signal to feed DAC0 SYNC input.
6.3.23
See
6.3.23.1
This bit field is reserved. Each bit must be set to 0.
6.3.23.2
This field selects the alternate input source signal to feed Quad Timer A, input 3.
6.3.23.3
This bit field is reserved. Each bit must be set to 0.
6.3.23.4
This field selects the alternate input source signal to feed Quad Timer A, input 2.
Freescale Semiconductor
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Section 6.3.21
Base + $1A
RESET
Read
Write
000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default)
001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input
010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input
011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input
100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input
101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input
11x = Reserved
0 = I/O pin (External) - Use Timer A3 input/output pin
1 = PWM SYNC (Internal) - Use PWM reload synchronization signal
0 = I/O pin (External) - Use Timer A2 input/output pin
1 = CMPBO (Internal) - Use Comparator B output
Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2)
Internal Peripheral Source Select Register 2 for Quad Timer A
(SIM_IPS2)
Select Peripheral Input Source for SYNC Input to DAC 0
(IPS1_DSYNC0)—Bits 2–0
Reserved—Bits 15–13
Select Peripheral Input Source for TA3 (IPS2_TA3)—Bit 12
Reserved—Bits 11–9
Select Peripheral Input Source for TA2 (IPS2_TA2)—Bit 8
15
0
0
for general information about Internal Peripheral Source Select registers.
14
0
0
13
0
0
IPS2_
TA3
12
0
56F8037/56F8027 Data Sheet, Rev. 7
11
0
0
10
0
0
9
0
0
IPS2_
TA2
8
0
7
0
0
6
0
0
5
0
0
IPS2_
TA1
4
0
3
0
0
2
0
0
Register Descriptions
1
0
0
0
0
0
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