MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 8

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.1.5
1.2 56F8037/56F8027 Description
The 56F8037/56F8027 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs).
It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller
with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
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— Full-duplex operation
— Master and slave modes
— Four-words-deep FIFOs available on both transmitter and receiver
— Programmable Length Transactions (2 to 16 bits)
One Inter-Integrated Circuit (I
— Operates up to 400kbps
— Supports both master and slave operation
— Supports both 10-bit address mode and broadcasting mode
One Freescale scalable controller area network (MSCAN) module
— Fully compliant with CAN protocol - Version 2.0 A/B
— Supports standard and extended data frames
— Supports data rate up to 1Mbps
— Five receive buffers and three transmit buffers
Three 16-bit Programmable Interval Timers (PITs)
Two analog Comparators (CMPs)
— Selectable input source includes external pins, DACs
— Programmable output polarity
— Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs
— Output falling and rising edge detection able to generate interrupts
Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources
Up to 53 General-Purpose I/O (GPIO) pins with 5V tolerance
Integrated Power-On Reset and Low-Voltage Interrupt Module
Phase Lock Loop (PLL) to provide high-speed clock to the core and peripherals
Clock sources:
— On-chip relaxation oscillator
— External clock: crystal oscillator, ceramic resonator and external clock source
JTAG/EOnCE debug programming interface for real-time debugging
Fabricated in high-density CMOS with 5V tolerance
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
Energy Information
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C) port
56F8037/56F8027 Data Sheet, Rev. 7
Freescale Semiconductor