ATTINY20-EK1 Atmel, ATTINY20-EK1 Datasheet - Page 87
ATTINY20-EK1
Manufacturer Part Number
ATTINY20-EK1
Description
KIT EVAL TOUCH ATTINY20
Manufacturer
Atmel
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-EK1
Sensor Type
*
Sensing Range
*
Interface
*
Sensitivity
*
Voltage - Supply
*
Embedded
*
Utilized Ic / Part
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
TinyAVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
ATtiny20
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
Tool Type
Development Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor To Be Evaluated
ATtiny20
Interface Type
Touch
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8235B–AVR–04/11
the counter value (TCNT1) matches either the OCR1A (WGM1[3:0] = 4) or the ICR1
(WGM1[3:0] = 12). The OCR1A or ICR1 define the top value for the counter, hence also its res-
olution. This mode allows greater control of the compare match output frequency. It also
simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
(TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter
(TCNT1) is cleared.
Figure 12-6. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing the TOP to a value close to BOTTOM when the counter is running with none or a low
prescaler value must be done with care since the CTC mode does not have the double buffering
feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the
counter will miss the compare match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many
cases this feature is not desirable. An alternative will then be to use the fast PWM mode using
OCR1A for defining TOP (WGM1[3:0] = 15) since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM1A[1:0] = 1). The OC1A value will not be visible on the port pin unless the data direction
for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum fre-
quency of f
the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
TCNTn
OCnA
(Toggle)
Period
clk_I/O
/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by
1
f
OCnA
2
=
---------------------------------------------------
2 N
⋅
3
⋅
(
f
1
clk_I/O
+
OCRnA
Figure 12-6 on page
4
)
87. The counter value
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnA[1:0] = 1)
ATtiny20
87
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