ATTINY20-EK1 Atmel, ATTINY20-EK1 Datasheet - Page 105

• Manufacturer Part Number: ATTINY20-EK1
• Description: KIT EVAL TOUCH ATTINY20
• Manufacturer: Atmel

Specifications of ATTINY20-EK1

• Sensor Type: *
• Sensing Range: *
• Interface: *
• Sensitivity: *
• Voltage - Supply: *
• Embedded: *
• Utilized Ic / Part: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: TinyAVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: ATtiny20
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• Tool Type: Development Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor To Be Evaluated: ATtiny20
• Interface Type: Touch
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. Timer/Counter Prescaler
13.1
13.2
8235B–AVR–04/11
Prescaler Reset
External Clock Source
Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counters. Tn
is used as a general name, n = 0, 1.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/CounterCounter, and it is shared by the Timer/Counter Tn. Since the prescaler is not
affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for
situations where a prescaled clock is used. One example of prescaling artifacts occurs when the
timer is enabled and clocked by the prescaler (CSn[2:0] = 2, 3, 4, or 5). The number of system
clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 sys-
tem clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
equivalent block diagram of the Tn synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
high period of the internal system clock.
The edge detector generates one clk
(CSn[2:0] = 6) edge it detects.
Figure 13-1. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
CLK_I/O
Tn
clk
I/O
/256, or f
D
LE
CLK_I/O
Q
/1024.
Synchronization
CLK_I/O
D
Q
). Alternatively, one of four taps from the prescaler can be used
T
0
pulse for each positive (CSn[2:0] = 7) or negative
clk
I/O
D
). The latch is transparent in the
Figure 13-1
Q
CLK_I/O
Edge Detector
shows a functional
ATtiny20
/8, f
CLK_I/O
Tn_sync
(To Clock
Select Logic)
Tn
). The
/64,
105