ATTINY20-EK1 Atmel, ATTINY20-EK1 Datasheet - Page 47

• Manufacturer Part Number: ATTINY20-EK1
• Description: KIT EVAL TOUCH ATTINY20
• Manufacturer: Atmel

Specifications of ATTINY20-EK1

• Sensor Type: *
• Sensing Range: *
• Interface: *
• Sensitivity: *
• Voltage - Supply: *
• Embedded: *
• Utilized Ic / Part: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: TinyAVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: ATtiny20
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• Tool Type: Development Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor To Be Evaluated: ATtiny20
• Interface Type: Touch
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.4
8235B–AVR–04/11
Reading the Pin Value
Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay.
shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted t
Figure 10-4. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
INSTRUCTIONS
SYSTEM CLK
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
PORTx
DDRx
Px0
Px1
r16
r17
PINxn
r17
0x01
tri-state
out DDRx, r16
Figure 10-2 on page
XXX
intermediate tri-state cycle
0x02
tri-state
nop
t
pd, max
0x02
0x01
0x55
0x00
XXX
45, the PINxn Register bit and the preced-
out DDRx, r17
t
pd, min
pd,max
in r17, PINx
and t
intermediate tri-state cycle
tri-state
0x01
pd,min
respectively.
ATtiny20
0xFF
Figure 10-4
47