ATTINY20-EK1 Atmel, ATTINY20-EK1 Datasheet - Page 116

• Manufacturer Part Number: ATTINY20-EK1
• Description: KIT EVAL TOUCH ATTINY20
• Manufacturer: Atmel

Specifications of ATTINY20-EK1

• Sensor Type: *
• Sensing Range: *
• Interface: *
• Sensitivity: *
• Voltage - Supply: *
• Embedded: *
• Utilized Ic / Part: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: TinyAVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: ATtiny20
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• Tool Type: Development Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor To Be Evaluated: ATtiny20
• Interface Type: Touch
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

116
ATtiny20
prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment
the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as
long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles, as summarised in
first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock
cycles in order to initialize the analog circuitry, as shown in
Figure 15-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of a first conversion. See
conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Sin-
gle Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again,
and a new conversion will be initiated on the first rising ADC clock edge.
Figure 15-5. ADC Timing Diagram, Single Conversion
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in
Figure 15-6
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
below. This assures a fixed delay from the trigger event to the start of conversion. In
1
1
2
MUX and REFS
Update
2
MUX and REFS
Update
12
3
13
Sample & Hold
4
14
5
15
6
Sample & Hold
16
First Conversion
17
7
One Conversion
18
8
19
9
20
10
Conversion
Complete
21
Figure 15-4
11
22
Conversion
Complete
23
12
Table 15-1 on page
24
13
below.
25
Figure
Sign and MSB of Result
Sign and MSB of Result
LSB of Result
Next Conversion
1
Next
Conversion
1
LSB of Result
15-5. When a
8235B–AVR–04/11
2
MUX and REFS
Update
2
MUX and REFS
Update
118. The
3
3