ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 32

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

www.national.com
2.2.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output
is activated such that OR+ goes high and OR- goes low. This
output is active as long as accurate data on either or both of
the buses would be outside the range of 00h to FFh.
2.2.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by
the value of the ADC's reference voltage. The reference volt-
age of the ADC08D1500 is derived from an internal band-gap
reference. The FSR pin controls the effective reference volt-
age of the ADC08D1500 such that the differential full-scale
input range at the analog inputs is a normal amplitude with
the FSR pin high, or a reduced amplitude with FSR pin low as
defined by the specification V
Characteristics. Best SNR is obtained with FSR high, but bet-
ter distortion and SFDR are obtained with the FSR pin low.
2.3 THE CLOCK INPUTS
The ADC08D1500 has differential LVDS clock inputs, CLK+
and CLK-, which must be driven with an a.c. coupled, differ-
ential clock signal. Although the ADC08D1500 is tested and
its performance is guaranteed with a differential 1.5 GHz
clock, it typically will function well with input clock frequencies
indicated in the Converter Electrical Characteristic. The clock
inputs are internally terminated and biased. The input clock
signal must be capacitively coupled to the clock pins as indi-
cated in Figure 14.
Operation up to the sample rates indicated in the Converter
Electrical Characteristic is typically possible if the maximum
ambient temperatures indicated are not exceeded. Operating
at higher sample rates than indicated for the given ambient
temperature may result in reduced device reliability and prod-
uct lifetime. This is because of the higher power consumption
and die temperatures at high sample rates. Important also for
reliability is proper thermal management . See 2.6.2 Thermal
Management.
The differential input clock line pair should have a character-
istic impedance of 100Ω and (when using a balun), be termi-
nated at the clock source in that (100Ω) characteristic
impedance. The input clock line should be as short and as
direct as possible. The ADC08D1500 clock input is internally
terminated with an untrimmed 100Ω resistor.
Insufficient input clock levels will result in poor dynamic per-
formance. Excessively high input clock levels could cause a
change in the analog input offset voltage. To avoid these
problems, keep the clock level within the range specified as
V
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC08D1500 fea-
tures a duty cycle clock correction circuit which can maintain
FIGURE 14. Differential (LVDS) Input Clock Connection
ID
in the Converter Electrical Characteristics.
IN
in the Converter Electrical
20152147
32
performance over temperature. The ADC will meet its perfor-
mance specification if the input clock high and low times are
maintained within the duty cycle range as specified in the
Converter Electrical Characteristics.
High speed, high performance ADCs such as the AD-
C08D1500 require a very stable input clock signal with mini-
mum phase noise or jitter. ADC jitter requirements are defined
by the ADC resolution (number of bits), maximum ADC input
frequency and the input signal amplitude relative to the ADC
input full scale range. The maximum jitter (the sum of the jitter
from all sources) allowed to prevent a jitter-induced reduction
in SNR is found to be
where t
V
full-scale range of the ADC, "N" is the ADC resolution in bits
and f
analog input.
Note that the maximum jitter described above is the RSS sum
of the jitter from all sources, including that in the ADC input
clock, that added by the system to the ADC input clock and
input signals and that added by the ADC itself. Since the ef-
fective jitter added by the ADC is beyond user control, the best
the user can do is to keep the sum of the externally added
input clock jitter and the jitter added by the analog circuitry to
the analog signal to a minimum.
Input clock amplitudes above those specified in the Converter
Electrical Characteristics may result in increased input offset
voltage. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
2.4 CONTROL PINS
Six control pins (without the use of the serial interface) provide
a wide range of possibilities in the operation of the AD-
C08D1500 and facilitate its use. These control pins provide
Full-Scale Input Range setting, Self Calibration, Calibration
Delay, Output Edge Synchronization choice, LVDS Output
Level choice and a Power Down feature.
2.4.1 Full-Scale Input Range Setting
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08D1500 will function with the CAL pin held
high at power up, but no calibration will be done and perfor-
mance will be impaired. A manual calibration, however, may
be performed after powering up with the CAL pin high. See .
2.4.2 Self Calibration
The ADC08D1500 self-calibration must be run to achieve
specified performance. The calibration procedure is run upon
power-up and can be run any time on command. The cali-
bration procedure is exactly the same whether there is an
input clock present upon power up or if the clock begins some
time after application of power. The CalRun output indicator
is high while a calibration is in progress. Note that the DCLK
outputs are not active during a calibration cycle, therefore it
is not recommended as a system clock.
IN(P-P)
IN
t
is the maximum input frequency, in Hertz, to the ADC
J(MAX)
J(MAX)
is the peak-to-peak analog input signal, V
= (V
is the rms total of all jitter sources in seconds,
INFSR
/ V
IN(P-P)
) x (1/(2
(N+1)
x
π
x f
INFSR
IN
))
is the