ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 25

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

tion on the falling edge of DCLK. See 2.4.3 Output Edge
Synchronization.
1.1.5.3 Double Data Rate
A choice of single data rate (SDR) or double data rate (DDR)
output is offered. With single data rate the output clock
(DCLK) frequency is the same as the data rate of the two out-
put buses. With double data rate the DCLK frequency is half
the data rate and data is sent to the outputs on both edges of
DCLK. DDR clocking is enabled in non-Extended Control
mode by allowing pin 4 to float.
1.1.6 The LVDS Outputs
The data outputs, the Out Of Range (OR) and DCLK, are
LVDS. Output current sources provide 3 mA of output current
to a differential 100 Ohm load when the OutV input (pin 3) is
high or 2.2 mA when the OutV input is low. For short LVDS
lines and low noise systems, satisfactory performance may
be realized with the OutV input low, which results in lower
power consumption. If the LVDS lines are long and/or the
system in which the ADC08D1500 is used is noisy, it may be
necessary to tie the OutV pin high.
The LVDS data output have a typical common mode voltage
of 800mV when the V
common mode voltage can be increased to 1.2V by tying the
V
IMPORTANT NOTE: Tying the V
crease the differential LVDS output voltage by up to 40 mV.
1.1.7 Power Down
The ADC08D1500 is in the active state when the Power Down
pin (PD) is low. When the PD pin is high, the device is in the
power down mode. In this power down mode the data output
pins (positive and negative) are TRI-STATE and the device
power consumption is reduced to a minimal level. The DCLK
+/- and OR +/- are not at TRI-STATE. They are weakly pulled
BG
pin to V
A
if a higher common mode is required.
BG
pin is unconnected and floating. This
BG
pin to V
A
will also in-
25
down to ground internally. Therefore when both I and Q are
powered down the DCLK +/- and OR +/- should not be termi-
nated to a DC voltage.
A high on the PDQ pin will power down the "Q" channel and
leave the "I" channel active. There is no provision to power
down the "I" channel independently of the "Q" channel. Upon
return to normal operation, the pipeline will contain meaning-
less information.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state. Calibration will
function with the "Q" channel powered down, but that channel
will not be calibrated if PDQ is high. If the "Q" channel is sub-
sequently to be used, it is necessary to perform a calibration
after PDQ is brought low.
1.2 NORMAL/EXTENDED CONTROL
The ADC08D1500 may be operated in one of two modes. In
the simpler standard control mode, the user affects available
configuration and control of the device through several control
pins. The "extended control mode" provides additional con-
figuration and control options through a serial interface and a
set of 9 registers. The two control modes are selected with
pin 14 (FSR/ECE: Extended Control Enable). The choice of
control modes is required to be a fixed selection and is not
intended to be switched dynamically while the device is op-
erational.
Table 2 shows how several of the device features are affected
by the control mode chosen.
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