ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 11

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

POWER SUPPLY CHARACTERISTICS
I
I
P
PSRR1
PSRR2
AC ELECTRICAL CHARACTERISTICS
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A
DR
CLK1
CLK2
CLK2
CL
CH
RS
RH
SD
RPW
LHT
HLT
OSK
SU
H
AD
AJ
OD
D
Symbol
Analog Supply Current
Output Driver Supply Current
Power Consumption
D.C. Power Supply Rejection
Ratio
A.C. Power Supply Rejection
Ratio
Maximum Input Clock Frequency Normal Mode (non DES) or DES Mode
Minimum Input Clock Frequency Normal Mode (non DES)
Minimum Input Clock Frequency DES Mode
Input Clock Duty Cycle
Input Clock Duty Cycle
Input Clock Low Time
Input Clock High Time
DCLK Duty Cycle
Reset Setup Time
Reset Hold Time
Synchronizing Edge to DCLK
Output Delay
Reset Pulse Width
Differential Low to High Transition
Time
Differential High to Low Transition
Time
DCLK to Data Output Skew
Data to DCLK Set-Up Time
DCLK to Data Hold Time
Sampling (Aperture) Delay
Aperture Jitter
Input Clock to Data Output Delay
(in addition to Pipeline Delay)
Pipeline Delay (Latency)
(Notes 11, 14)
Parameter
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
Change in Full Scale Error with change
in V
248 MHz, 50mV
200 MHz
GHz (Normal Mode) (Note 12)
500MHz
GHz (DES Mode) (Note 12)
(Note 11)
(Note 11)
(Note 11)
(Note 11)
(Note 11)
(Note 11)
10% to 90%, C
10% to 90%, C
50% of DCLK transition to 50% of Data
transition, SDR Mode
and DDR Mode, 0° DCLK (Note 11)
DDR Mode, 90° DCLK (Note 11)
DDR Mode, 90° DCLK (Note 11)
Input CLK+ Fall to Acquisition of Data
50% of Input Clock transition to 50% of
Data transition
DI Outputs
DId Outputs
DQ Outputs
DQd Outputs
A
from 1.8V to 2.0V
≤
≤
Input clock frequency
Input clock frequency
Conditions
L
L
P-P
= 2.5 pF
= 2.5 pF
11
riding on V
Normal Mode
DES Mode
Normal Mode
DES Mode
A
≤
≤
1.5
1.5
t
OD
(Note 8)
Typical
0.012
770
524
207
116
200
500
333
333
150
250
250
250
±50
400
560
1.8
1.8
1.2
3.5
1.7
1.3
0.4
3.1
30
51
50
50
50
+ t
OSK
(Note 8)
Limits
1.45
13.5
14.5
870
600
290
165
133
133
2.2
1.5
20
80
20
80
45
55
13
14
13
14
4
Clock Cycles
Input Clock
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GHz (min)
mA (max)
mA (max)
mA (max)
mA (max)
ps (max)
W (max)
W (max)
% (max)
% (max)
% (max)
(Limits)
ps (min)
ps (min)
% (min)
% (min)
% (min)
ps rms
Cycles
Units
(min)
MHz
MHz
mW
mA
mA
dB
dB
ps
ps
ps
ps
ns
ns
ns
ns