ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 29

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

Bit 14
Bits 13:0
Bit 15
Addr: Dh (1101b)
Addr: Eh (1110b)
DEN ACP
D15
D15
Bit 15
Bit 14
D7
D7
IS
1
1
ADS
D14
D14
D6
D6
1
1
DES Enable. Setting this bit to 1b enables the
Dual Edge Sampling mode. In this mode the
ADCs in this device are used to sample and
convert the same analog input in a time-
interleaved manner, accomplishing a sample
rate of twice the input clock rate. When this bit
is set to 0b, the device operates in the normal
dual channel mode.
POR State: 0b
Automatic Clock Phase (ACP) Control. Setting
this bit to 1b enables the Automatic Clock
Phase Control. In this mode the DES Coarse
and Fine manual controls are disabled. A
phase detection circuit continually adjusts the
I and Q sampling edges to be 180 degrees out
of phase. When this bit is set to 0b, the sample
(input) clock delay between the I and Q
channels is set manually using the DES
Coarse and Fine Adjust registers. (See
Section 2.4.5 for important application
information) Using the ACP Control option
is recommended over the manual DES
settings.
POR State: 0b
Must be set to 1b
Input Select. When this bit is set to 0b the "I"
input is operated upon by both ADCs. When
this bit is set to 1b the "Q" input is operated on
by both ADCs.
POR State: 0b
Adjust Direction Select. When this bit is set to
0b, the programmed delays are applied to the
"I" channel sample clock while the "Q" channel
sample clock remains fixed. When this bit is
set to 1b, the programmed delays are applied
to the "Q" channel sample clock while the "I"
channel sample clock remains fixed.
POR State: 0b
D13
D13
D5
D5
1
1
1
DES Coarse Adjust
DES Enable
CAM
D12
D12
D4
D4
1
1
1
D11
D11
D3
D3
1
1
1
D10
D10
D2
D2
W only (0x3FFF)
1
1
1
1
W only (0x07FF)
D9
D1
D9
D1
1
1
1
1
D8
D0
D8
D0
1
1
1
1
29
1.4.1 Note Regarding Extended Mode Offset Correction
When using the I or Q channel Offset Adjust registers, the
following information should be noted.
For offset values of +0000 0000 and -0000 0000, the actual
offset is not the same. By changing only the sign bit in this
case, an offset step in the digital output code of about 1/10th
of an LSB is experienced. This is shown more clearly in the
Figure below.
(MSB)
Bits 15:7
Bits 13:11 Coarse Adjust Magnitude. Each code value in
Bits 10:0 Must be set to 1b
Addr: Fh (1111b)
(LSB)
D15
Bit 6:0
D7
FIGURE 10. Extended Mode Offset Behavior
D14
D6
this field delays either the "I" channel or the "Q"
channel sample clock (as determined by the
ADS bit) by approximately 20 picoseconds. A
value of 000b in this field causes zero
adjustment.
POR State: 000b
Fine Adjust Magnitude. Each code value in this
field delays either the "I" channel or the "Q"
channel sample clock (as determined by the
ADS bit of the DES Coarse Adjust Register) by
approximately 0.1 ps. A value of 0000 0000 0b
in this field causes zero adjustment. Note that
the amount of adjustment achieved with each
code will vary with the device conditions as
well as with the Coarse Adjustment value
chosen.
POR State: 0000 0000 0b
Must be set to 1b
1
D13
D5
1
DES Fine Adjust
D12
D4
1
D11
D3
1
FAM
D10
W only (0x007F)
D2
1
D9
D1
1
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D8
D0
1
20152130