ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 30

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

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1.5 MULTIPLE ADC SYNCHRONIZATION
The ADC08D1500 has the capability to precisely reset its
sampling clock input to DCLK output relationship as deter-
mined by the user-supplied DCLK_RST pulse. This allows
multiple ADCs in a system to have their DCLK (and data) out-
puts transition at the same time with respect to the shared
CLK input that all the ADCs use for sampling.
The DCLK_RST signal must observe some timing require-
ments that are shown in Figure 6, Figure 7and Figure 8 of the
Timing Diagrams. The DCLK_RST pulse must be of a mini-
mum width and its deassertion edge must observe setup and
hold times with respect to the CLK input rising edge. These
timing specifications are listed as t
Converter Electrical Characteristics.
The DCLK_RST signal can be asserted asynchronous to the
input clock. If DCLK_RST is asserted, the DCLK output is held
in a designated state. The state in which DCLK is held during
the reset period is determined by the mode of operation (SDR/
DDR) and the setting of the Output Edge configuration pin or
bit. (Refer to Figure 6,Figure 7 and Figure 8 for the DCLK
reset state conditions). Therefore, depending upon when the
DCLK_RST signal is asserted, there may be a narrow pulse
on the DCLK line during this reset event. When the
DCLK_RST signal is de-asserted in synchronization with the
CLK rising edge, the next CLK falling edge synchronizes the
DCLK output with those of other ADC08D1500s in the sys-
tem. The DCLK output is enabled again after a constant delay
(relative to the input clock frequency) which is equal to the
CLK input to DCLK output delay (t
hibits this delay characteristic in normal operation.
The DCLK_RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration.
2.0 Applications Information
2.1 THE REFERENCE VOLTAGE
The voltage reference for the ADC08D1500 is derived from a
1.254V bandgap reference, a buffered version of which is
made available at pin 31, V
output has an output current capability of ±100 μA and should
be buffered if more current than this is required.
The internal bandgap-derived reference voltage has a nomi-
nal value of V
in 1.1.4 The Analog Inputs.
There is no provision for the use of an external reference volt-
age, but the full-scale input voltage can be adjusted through
a Configuration Register in the Extended Control mode, as
explained in 1.2 NORMAL/EXTENDED CONTROL.
Differential input signals up to the chosen full-scale level will
be digitized to 8 bits. Signal excursions beyond the full-scale
range will be clipped at the output. These large signal excur-
sions will also activate the OR output for the time that the
signal is out of range. See 2.2.2 Out Of Range (OR) Indica-
tion.
One extra feature of the V
the common mode voltage level of the LVDS outputs. The
output offset voltage (V
pin is used as an output or left unconnected. To raise the
LVDS offset voltage to a typical value of 1200mV the V
can be connected directly to the supply rails.
IN
, as determined by the FSR pin and described
OS
BG
) is typically 800mV when the V
pin is that it can be used to raise
BG
, for user convenience. This
SD
RH
). The device always ex-
, t
RS
, and t
RPW
BG
in the
pin
BG
30
2.2 THE ANALOG INPUT
The analog input is a differential one to which the signal
source may be a.c. coupled or d.c. coupled. In the normal
mode, the full-scale input range is selected using the FSR pin
as specified in the Converter Electrical Characteristics. In the
Extended Control mode, the full-scale input range is selected
by programming the Full-Scale Voltage Adjust register
through the Serial Interface. For best performance when ad-
justing the input full-scale range in the Extended Control, refer
to 1.4 REGISTER DESCRIPTION. for guidelines on limiting
the amount of adjustment.
Table 5 gives the input to output relationship with the FSR pin
high when the normal (non-extended) mode is used. With the
FSR pin grounded, the millivolt values; in are reduced to 75%
of the values indicated. In the Extended Control Mode, these
values will be determined by the full scale range and offset
settings in the Control Registers.
The buffered analog inputs simplify the task of driving these
inputs and the RC pole that is generally used at sampling ADC
inputs is not required. If it is desired to use an amplifier circuit
before the ADC, use care in choosing an amplifier with ade-
quate noise and distortion performance and adequate gain at
the frequencies used for the application.
Note that a precise d.c. common mode voltage must be
present at the ADC inputs. This common mode voltage,
V
and the input signal is a.c. coupled to the ADC.
When the inputs are a.c. coupled, the V
grounded, as shown in Figure 11. This causes the on-chip
V
50k-Ohm resistors.
IMPORTANT NOTE: An Analog input channel that is not used
(e.g. in DES Mode) should be left floating when the inputs are
a.c. coupled. Do not connect an unused analog input to
ground.
When the d.c. coupled mode is used, a common mode volt-
age must be provided at the differential inputs. This common
CMO
CMO
V
V
V
V
CM
CM
CM
CM
, is provided on-chip when a.c. input coupling is used
TABLE 5. DIFFERENTIAL INPUT TO OUTPUT
voltage to be connected to the inputs through on-chip
− 217.5mV
+ 217.5mV
− 109 mV
+ 109 mV
V
V
(Non-Extended Control Mode, FSR High)
IN
CM
+
FIGURE 11. Differential Input Drive
V
V
RELATIONSHIP
V
V
CM
CM
CM
CM
+ 217.5mV
− 217.5mV
+ 109 mV
V
−109 mV
V
IN
CM
−
20152144
CMO
Output Code
0111 1111 /
0000 0000
0100 0000
1000 0000
1100 0000
1111 1111
output must be