ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 26

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

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The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 3.
Dual Edge Sampling (DES)
SDR or DDR Clocking
DDR Clock Phase
SDR Data transitions with rising or falling
DCLK edge
LVDS output level
Power-On Calibration Delay
Full-Scale Range
Input Offset Adjust
Dual Edge Sampling Selection
Dual Edge Sampling Input Channel
Selection
DES Sampling Clock Adjustment
LVDS Output Amplitude
SDR or DDR Clocking
Input Offset Adjust
TABLE 3. Extended Control Mode Operation
DDR Clock Phase
Full-Scale Range
Calibration Delay
Feature
Feature
(Pin 14 Floating)
Extended Control Mode
Data changes with DCLK
700 mV nominal for both
No adjustment for either
Normal amplitude
edge (0° phase)
DDR Clocking
Default State
Not enabled
(710 mV
Short Delay
channels
channel
DDR Clocking selected with pin 4
floating. SDR clocking selected when pin
4 not floating.
Not Selectable (0° Phase Only)
SDR Data transitions with rising edge of
DCLK+ when pin 4 is high and on falling
edge when low.
Normal differential data and DCLK
amplitude selected when pin 3 is high
and reduced amplitude selected when
low.
Short delay selected when pin 127 is low
and longer delay selected when high.
Normal input full-scale range selected
when pin 14 is high and reduced range
when low. Selected range applies to both
channels.
Not possible
Enabled with pin 127
Only I-Channel Input can be used
The Clock Phase is adjusted
automatically
P-P
TABLE 2. Features and Modes
)
Normal Control Mode
26
1.3 THE SERIAL INTERFACE
IMPORTANT NOTE: During the initial write using the serial
interface, all 8 user registers must be written with desired or
default values. In addition, the first write to the DES Enable
register (Dh) must load the default value (0x3FFFh). Once all
registers have been written once, other desired settings, in-
cluding enabling DES can be loaded.
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS) Eight write only registers are acces-
sible through this serial interface.
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK: Serial data input is accepted with the rising edge of
this signal. There is no minimum frequency requirement for
SCLK.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram.
Selected with nDE in the Configuration
Register (1h; bit-10). When the device is
in DDR mode, address 1h, bit-8 must be
set to 0b.
Selected with DCP in the Configuration
Register (1h; bit-11).
Selected with OE in the Configuration
Register (1h; bit-8).
Selected with the OV in the
Configuration Register (1h; bit-9).
Short delay only.
Up to 512 step adjustments over a
nominal range specified in 1.4
REGISTER DESCRIPTION. Selected
using the Input Full-Scale Adjust register
(3h; bits-7 thru 15).
512 steps of adjustment using the Input
Offset register (2h; bits-7 thru 15) as
specified in
Enabled through DES Enable Register.
Either I- or Q-Channel input may be
sampled by both ADCs.
Automatic Clock Phase control can be
selected by setting bit 14 in the DES
Enable Register (Dh). The clock phase
can also be adjusted manually through
the Coarse & Fine Registers (Eh and
Fh).
Extended Control Mode