ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 28

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

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Bit 8
Bits 7:0
Bits 15:8
Bit 7
Bit 6:0
Bit 15:7
(MSB)
Addr: 2h (0010b)
(MSB)
Addr: 3h (0011b)
(LSB)
Bits 6:0
Sign
D15
D15
D7
D7
D14
I-Channel Full-Scale Voltage Adjust
D6
1
D14
D6
OE: Output Edge. This bit selects the DCLK
edge with which the data words transition in
the SDR mode and has the same effect as the
OutEdge pin in the normal control mode.
When this bit is 1, the data outputs change with
the rising edge of DCLK+. When this bit is 0,
the data output change with the falling edge of
DCLK+.
POR State: 0b
Must be set to 1b.
Offset Value. The input offset of the I-Channel
ADC is adjusted linearly and monotonically by
the value in this field. 00h provides a nominal
zero offset, while FFh provides a nominal 45
mV of offset. Thus, each code step provides
0.176 mV of offset.
POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Must be set to 1b
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
0000 0000 0
1000 0000 0
Default Value
1111 1111 1
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
1
D13
D5
D13
1
D5
1
I-Channel Offset
Offset Value
D12
D4
D12
1
D4
1
Adjust Value
D11
560mV
700mV
840mV
D3
1
D11
P-P
D3
1
differential value.
D10
P-P
P-P
P-P
D2
D10
1
W only (0x007F)
W only (0x807F)
D2
1
D9
D1
1
D9
D1
1
(LSB)
D8
D0
1
D8
D0
1
28
Bit 15:8
Bit 7
Bit 6:0
Bit 15:7
Bits 6:0
(MSB)
Addr: Ah (1010b)
Addr: Bh (1011b)
(MSB)
(LSB)
Sign
D15
D15
D7
D7
Q-Channel Full-Scale Voltage Adjust
D14
D6
D14
1
D6
Offset Value. The input offset of the Q-
Channel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal 45 mV of offset. Thus,
each code step provides about 0.176 mV of
offset.
POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Must be set to 1b
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
0000 0000 0
1000 0000 0
1111 1111 1
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
1
D13
D5
D13
1
D5
1
Q-Channel Offset
Offset Value
D12
D4
D12
1
D4
1
Adjust Value
D11
560mV
700mV
840mV
D3
1
D11
P-P
D3
1
differential value.
D10
P-P
P-P
P-P
D2
D10
1
W only (0x007F)
W only (0x807F)
D2
1
D9
D1
1
D9
D1
1
(LSB)
D8
D0
1
D8
D0
1