EVB9303 SMSC, EVB9303 Datasheet - Page 57

• Manufacturer Part Number: EVB9303
• Description: EVALUATION BOARD FOR LAN9303
• Manufacturer: SMSC

Specifications of EVB9303

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9303
• Primary Attributes: 3 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: Full Duplex and HP Auto-MDIX Support, 10BASE-T and 100BASE-TX
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1095

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
5.2.1
5.2.2
Switch Fabric Interrupts
Multiple Switch Fabric interrupt sources are provided in a three-tiered register structure as shown in
Figure
Register (INT_STS)
Global Interrupt Pending Register
The
(SWE_IMR)
Manager, Switch Engine, and Port 2,1,0 MACs).
The low-level Switch Fabric sub-module interrupt pending and mask registers of the Buffer Manager,
Switch Engine, and Port 2,1,0 MACs provide multiple interrupt sources from their respective sub-
modules. These low-level registers provide the following interrupt sources:
In order for a Switch Fabric interrupt event to trigger the external IRQ interrupt pin, the following must
be configured:
For additional details on the Switch Fabric interrupts, refer to
on page
Ethernet PHY Interrupts
The Port 1 and Port 2 PHYs each provide a set of identical interrupt sources. The top-level
Interrupt Event (PHY_INT1)
Register (INT_STS)
Interrupt Source Flags Register
Port 1 and Port 2 PHY interrupts are enabled/disabled via their respective
Register
via the
Port 2 PHYs are each capable of generating unique interrupts based on the following events:
—Status B Pending
—Status A Pending
—Interrupt Pending
—No currently supported interrupt sources. These registers are reserved for future use.
Buffer Manager
Pending Register
Switch Engine
Pending Register
Port 2,1,0 MACs
Pending Register
The desired Switch Fabric sub-module interrupt event must be enabled in the corresponding mask
register
Interrupt Mask Register (SWE_IMR)
Register (MAC_IMR_x)
The desired Switch Fabric sub-module interrupt event must be enabled in the
Interrupt Mask Register (SW_IMR)
Switch Fabric Interrupt Event Enable (SWITCH_INT_EN)
(INT_EN)
IRQ output must be enabled via the
Register (IRQ_CFG)
ENERGYON Activated
Auto-Negotiation Complete
Remote Fault Detected
Link Down (Link Status Negated)
Switch Engine Interrupt Pending Register (SWE_IPR)
5.1. The top-level
Port x PHY Interrupt Source Flags Register
87.
(PHY_INTERRUPT_MASK_x). The source of a PHY interrupt can be determined and cleared
(Buffer Manager Interrupt Mask Register (BM_IMR)
provide status and enabling/disabling of all Switch Fabric sub-modules interrupts (Buffer
must be set
(Switch Engine Interrupt Mask Register (SWE_IMR)
provide indication that a PHY interrupt event occurred in the respective
(Buffer Manager Interrupt Mask Register (BM_IMR)
provides indication that a Switch Fabric interrupt event occurred in the
(BM_IPR))
(SWE_IPR))
(MAC_IPR_x))
(Port x MAC Interrupt Mask Register (MAC_IMR_x)
Switch Fabric Interrupt Event (SWITCH_INT)
for the Port 2,1,0 MACs)
and
(PHY_INTERRUPT_SOURCE_x).
Port 2 PHY Interrupt Event (PHY_INT2)
(SW_IPR).
DATASHEET
for the Switch Engine, and/or
IRQ Enable (IRQ_EN)
57
(PHY_INTERRUPT_SOURCE_x). The Port 1 and
and
bit of the
Section 6.6, "Switch Fabric Interrupts,"
for the Buffer Manager,
Switch Engine Interrupt Mask Register
bit of the
Port x MAC Interrupt Mask
Interrupt Enable Register
and
and
Interrupt Configuration
and
bit of the
bits of the
Port x PHY Interrupt Mask
Buffer Manager Interrupt
Switch Engine Interrupt
Port x MAC Interrupt
Revision 1.4 (07-07-10)
Switch Global
Interrupt Status
Interrupt Status
Switch Engine
Port 1 PHY
Port x PHY
Switch