EVB9303 SMSC, EVB9303 Datasheet
EVB9303
Specifications of EVB9303
Related parts for EVB9303
EVB9303 Summary of contents
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... Programmable broadcast storm protection with global % control and enable per port — Programmable buffer usage limits — Dynamic queues on internal memory — Programmable filter by MAC address SMSC LAN9303/LAN9303i LAN9303/LAN9303i Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’ ...
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... Port 1 & 2 PHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Chapter 5 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2.1 Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2.2 Ethernet PHY Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2.3 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.2.4 General Purpose Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.2.5 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.2.6 Device Ready Interrupt SMSC LAN9303/LAN9303i 3 DATASHEET Revision 1.4 (07-07-10) ...
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... Transmit Driver ..................................................................................................................................................................................... 92 7.2.1.6 100M Phase Lock Loop (PLL) ........................................................................................................................................................................ 92 7.2.2 100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.2.1 A/D Converter ................................................................................................................................................................................................. 93 7.2.2.2 DSP: Equalizer, BLW Correction and Clock/Data Recovery .......................................................................................................................... 93 Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 4 DATASHEET Datasheet SMSC LAN9303/LAN9303i ...
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... EEPROM Valid Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.4.3 MAC Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.4.4 Soft-Straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.4.4.1 PHY Registers Synchronization.................................................................................................................................................................... 115 8.4.4.2 Virtual PHY Registers Synchronization......................................................................................................................................................... 116 8.4.4.3 LED and Manual Flow Control Register Synchronization ............................................................................................................................. 116 8.4.5 Register Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SMSC LAN9303/LAN9303i 5 DATASHEET Revision 1.4 (07-07-10) ...
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... Interrupt Status Register (INT_STS)............................................................................................................................................................. 142 13.2.1.3 Interrupt Enable Register (INT_EN).............................................................................................................................................................. 143 13.2.2 GPIO/LED 144 13.2.2.1 General Purpose I/O Configuration Register (GPIO_CFG) .......................................................................................................................... 144 Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 6 DATASHEET Datasheet SMSC LAN9303/LAN9303i ...
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... Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x)........................................................................................ 242 13.4.2.17 Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x) ............................................................................................. 243 13.4.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) ...................................................................................... 244 13.4.2.19 Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x) ..................................................................................... 245 SMSC LAN9303/LAN9303i 7 DATASHEET Revision 1.4 (07-07-10) ...
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... Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA) ........................................................... 327 13.4.4.12 Buffer Manager Random Discard Table Read Data Register (BM_RNDM_DSCRD_TBL_RDATA)............................................................ 328 13.4.4.13 Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) ................................................................................................... 329 Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 8 DATASHEET Datasheet SMSC LAN9303/LAN9303i ...
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... Turbo MII Interface Timing (PHY Mode 359 14.5.8 RMII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 14.5.9 SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 14.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Chapter 15 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 15.1 56-QFN Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Chapter 16 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 SMSC LAN9303/LAN9303i 9 DATASHEET Revision 1.4 (07-07-10) ...
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... Figure 14.13RMII P0_OUTCLK Input Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Figure 14.14SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Figure 15.1 56-QFN Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Figure 15.2 56-QFN Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 10 DATASHEET Datasheet SMSC LAN9303/LAN9303i ...
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... Table 14.4 I/O Buffer Characteristics 348 Table 14.5 100BASE-TX Transceiver Characteristics 349 Table 14.6 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Table 14.7 nRST Reset Pin Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Table 14.8 Power-On Configuration Strap Latching Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 SMSC LAN9303/LAN9303i 11 DATASHEET Revision 1.4 (07-07-10) ...
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... Table 14.18RMII P0_OUTCLK Input Mode Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Table 14.19SMI Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Table 14.20Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Table 15.1 56-QFN Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Table 16.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 12 DATASHEET Datasheet SMSC LAN9303/LAN9303i ...
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... Level-Triggered Sticky Bit lsb LSB MDI MDIX MII MIIM SMSC LAN9303/LAN9303i 10BASE-T (10Mbps Ethernet, IEEE 802.3) 100BASE-TX (100Mbps Fast Ethernet, IEEE 802.3u) Analog-to-Digital Converter Address Logic Resolution Baseline Wander Buffer Manager - Part of the switch fabric Bridge Protocol Data Unit - Messages which carry the Spanning Tree ...
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... Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an Ethernet frame. Serial In Parallel Out Serial Management Interface Signal Quality Error (also known as “heartbeat”) Start of Stream Delimiter User Datagram Protocol - A connectionless protocol run on top of IP networks Universally Unique IDentifier 16-bits 14 DATASHEET Datasheet SMSC LAN9303/LAN9303i ...
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... Targeted applications include: set top boxes (cable, satellite and IP), digital televisions, digital video recorders, voice over IP and video phone systems, home gateways, and test and measurement equipment. SMSC LAN9303/LAN9303i 2 C managed. This flexibility in management makes ...
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Block Diagram MDIO Ethernet 10/100 10/100 PHY MII MAC Registers Switch Engine Buffer Manager 10/100 MII MAC Ethernet 10/100 PHY MDIO Registers GPIO/LED Controller LAN9303/ LAN9303i To optional GPIOs/LEDs MII/Turbo MII to PHY or MII/RMII/Turbo MII to MAC MII ...
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... Quality of Service (QoS) packet prioritization by VLAN tag, destination address, and port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. A 512 entry forwarding table provides ample room for MAC address forwarding tables. SMSC LAN9303/LAN9303i 17 DATASHEET Section 2.3, "Modes of ...
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... C-Bus Specification. A list of management modes and configurations settings Section 2.3, "Modes of Operation" master module which interfaces an optional external EEPROM with 2 C-Bus Specification. 18 DATASHEET Datasheet Operation"). The PMI 2 C slave serial interface (start and stop 2 C slave controller Section 2.3, "Modes SMSC LAN9303/LAN9303i ...
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... When an EEPROM is connected, the EEPROM loader can be used to load the initial device configuration from the external EEPROM via the I 2 can use the I C interface to read or write the EEPROM. SMSC LAN9303/LAN9303i Figure 2.4 displays a typical system configuration for each Chapter 9, "MII Data Interface," interface ...
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... MAC Figure 2.3 MII/RMII PHY Mode 2 C interface or the SMI/MIIM (Media Independent 2 C slave. The slave mode is used as a register access path for master EEPROM interface are shared interfaces. 20 DATASHEET Datasheet EEPROM (optional) Modes" EEPROM (optional) 2 C). The slave SMSC LAN9303/LAN9303i ...
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... I C master used to load initial configuration from EEPROM and for CPU R/W access to EEPROM slave used for management SMSC LAN9303/LAN9303i Table 2.1. System configuration diagrams for each mode are Table 2.1 Device Modes SMI/MIIM P0_MODE[2:0] INTERFACE STRAP VALUE SMI/MIIM slave, 000 ...
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... Microcontroller 22 DATASHEET Datasheet SMI Managed LAN9303/ LAN9303i EEPROM EEPROM slave (optional) MIIM/ MII SMI RMII/ SMI/MIIM MII 10/100 Microprocessor/ MAC Microcontroller Managed LAN9303/ LAN9303i EEPROM EEPROM slave (optional) MIIM/ MII SMI RMII/ MIIM MII Ethernet 10/100 Microprocessor/ MAC Microcontroller SMSC LAN9303/LAN9303i ...
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... RXP2 53 RXN2 54 VDD33A2 55 TXP2 56 NOTE: When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa NOTE: Exposed pad (VSS) on bottom of package must be connected to ground SMSC LAN9303/LAN9303i SMSC 56 PIN QFN (TOP VIEW) VSS Figure 3.1 Pin Assignments (TOP VIEW) 23 DATASHEET LED1/GPIO1/AMDIX2_LED1P 28 ...
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... Miscellaneous Pins PLL Pins Core and I/O Power and Ground Pins Note: A list of buffer type definitions is provided in Note: Please refer to the LAN9303/LAN9303i Reference Schematic and LANCheck Schematic Checklist on the SMSC website for additional connection information. NUM PINS NAME SYMBOL Port 1 Ethernet ...
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... Power 1 Supply Port 1 VDD18TX1 Transmitter 1 +1.8V Power Supply Note 3.3 Please refer to the LAN9303/LAN9303i Reference Schematic and LANCheck Schematic Checklist on the SMSC website for additional connection information. NUM PINS NAME SYMBOL Port 0 MII Input 1 P0_IND3 Data 3 SMSC LAN9303/LAN9303i BUFFER TYPE AI Used for internal bias circuits ...
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... Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). 26 DATASHEET Datasheet DESCRIPTION Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate Virtual PHY Basic (VPHY_BASIC_CTRL). Isolate (VPHY_ISO) bit is set in SMSC LAN9303/LAN9303i ...
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... Clock Port 0 MII P0_OUTD3 Output Data 3 1 Port 0 Duplex DUPLEX_POL_0 Polarity Configuration Strap SMSC LAN9303/LAN9303i BUFFER TYPE DESCRIPTION IS MII MAC Mode: This pin is the RX_ER signal from the external PHY and indicates a receive error in (PD) the packet. IS MII PHY Mode: This pin is the TX_ER signal from ...
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... IS This strap configures the mode for Port 0. See Note 3.4. (PU) Note 3.5 Please refer to the mode encoding details. 28 DATASHEET Datasheet DESCRIPTION Isolate (VPHY_ISO) bit P0_MODE0 strap entry for Isolate (VPHY_ISO) bit Isolate (VPHY_ISO) bit P0_MODE0 strap entry for SMSC LAN9303/LAN9303i ...
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... Port 0 Mode[0] P0_MODE0 Configuration Strap Port 0 MII 1 Output Data P0_OUTDV Valid SMSC LAN9303/LAN9303i BUFFER TYPE DESCRIPTION O8 MII MAC Mode: This pin is the transmit data 0 bit from the switch to the external PHY. O8 MII PHY Mode: This pin is the receive data 0 bit from the switch to the external MAC. The output ...
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... RMII PHY Mode: This pin is not used. 30 DATASHEET Datasheet DESCRIPTION Isolate (VPHY_ISO) bit is set in RMII/Turbo MII Clock Strength bit bit in the Virtual PHY Special bit is set in the Virtual PHY (VPHY_BASIC_CTRL). RMII/Turbo MII Clock Strength bit is set in the Isolate (VPHY_ISO) bit is set SMSC LAN9303/LAN9303i ...
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... EEPROM Loader. Please refer to 4.2.4, "Configuration Straps," on page 45 Note 3.5 An external supplemental pull-up may be needed, depending upon the input current loading of the external MAC/PHY device. SMSC LAN9303/LAN9303i BUFFER TYPE IS MII MAC Mode: This pin is an input from the external PHY indicating a network carrier ...
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... LED to VDD is used as the pull-up. 32 DATASHEET Datasheet DESCRIPTION LED Configuration is set. The buffer type LED Function 1-0 field in the LED Configuration and is configured to be either strap value sampled at reset. LED Configuration is clear. The pin is fully and the General Purpose (GPIO_DATA_DIR). SMSC LAN9303/LAN9303i ...
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... LED 4 LED4 GPIO 4 GPIO4 1 Serial MNGT1_LED4P Management Mode[1] and LED 4 Polarity Configuration Strap SMSC LAN9303/LAN9303i BUFFER TYPE DESCRIPTION O12/ This pin is configured to operate as an LED when the LED 4 Enable bit in the OD12/ Register (LED_CFG) OS12 depends on the setting of the (LED_FUN[1:0]) field in the ...
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... LED to VDD is used as the pull-up. 34 DATASHEET Datasheet DESCRIPTION LED Configuration is set. The buffer type LED Function 1-0 field in the LED Configuration and is configured to be either strap value sampled at reset. LED Configuration is clear. The pin is fully and the General Purpose (GPIO_DATA_DIR). SMSC LAN9303/LAN9303i ...
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... SYMBOL LED 2 LED2 GPIO 2 GPIO2 1 EEPROM Size E2PSIZE_LED2P and LED 2 Polarity Configuration Strap SMSC LAN9303/LAN9303i BUFFER TYPE DESCRIPTION O12/ This pin is configured to operate as an LED when the LED 2 Enable bit in the OD12/ Register (LED_CFG) OS12 depends on the setting of the (LED_FUN[1:0]) field in the ...
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... LED to VDD is used as the pull-up. 36 DATASHEET Datasheet DESCRIPTION LED Configuration is set. The buffer type LED Function 1-0 field in the LED Configuration and is configured to be either strap value sampled at reset. LED Configuration is clear. The pin is fully and the General Purpose (GPIO_DATA_DIR). Note 3.6. SMSC LAN9303/LAN9303i ...
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... GPIO/LED and Auto-MDIX operation listed in configuration strap pins are associated with Port 0 and control its operation. They are described in EEPROM Loader. Please refer to further information. SMSC LAN9303/LAN9303i BUFFER TYPE O12/ This pin is configured to operate as an LED when ...
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... This pin must be pulled- external resistor at all times clock input/open-drain This pin must be pulled- external resistor at all times clock input This pin must be pulled- external resistor at all times. for additional information DESCRIPTION Interrupt Configuration (IRQ_CFG). Please refer to Chapter 5, for further details. 351. SMSC LAN9303/LAN9303i ...
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... Power Supply 1 Crystal Input 1 1 Crystal Output Note 3.7 Please refer to the LAN9303/LAN9303i Reference Schematic and LANCheck Schematic Checklist on the SMSC website for additional connection information. Table 3.9 Core and I/O Power and Ground Pins NUM PINS NAME SYMBOL +3.3V I/O VDD33IO ...
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... GPIO4/ MNGT1_LED4P LED3 GPIO3/ MNGT0_LED3P LED2/ 41 VDD18PLL GPIO2/ E2PSIZE_LED2P LED1/ 42 TXN1 GPIO1/ AMDIX2_LED1P EXPOSED PAD MUST BE CONNECTED TO VSS 40 DATASHEET Datasheet PIN NUM PIN NAME 43 TXP1 44 VDD33A1 45 RXN1 46 RXP1 47 VDD33A1 48 VDD18TX1 49 EXRES 50 VDD33BIAS 51 VDD18TX2 52 VDD33A2 XI 53 RXP2 54 RXN2 55 VDD33A2 56 TXP2 SMSC LAN9303/LAN9303i ...
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... When connected to a load that must be pulled low, an external resistor must be added. AI Analog input AIO Analog bi-directional ICLK Crystal oscillator input pin OCLK Crystal oscillator output pin P Power pin SMSC LAN9303/LAN9303i Table 3.11 Buffer Types DESCRIPTION 41 DATASHEET Revision 1.4 (07-07-10) ...
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... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII Section 14.6, "Clock Circuit," on page for additional details. Table 14.20, “Crystal Specifications,” on page for detailed information on the usage of these straps. for additional information. 42 DATASHEET Datasheet 364. Optionally, this clock can Chapter 11, "General Purpose 364. SMSC LAN9303/LAN9303i ...
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... Driving the nRST input pin low initiates a chip-level reset. This event resets all circuitry within the device. Use of this reset input is optional, but when used, it must be driven for the period of time specified in Section 14.5.2, "Reset and Configuration Strap Timing," on page are latched, and the EEPROM Loader is run as a result of this reset. SMSC LAN9303/LAN9303i ...
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... Datasheet for a description of the nRST pin. Byte Order Test Device Ready until it is set. When set, the Device (HW_CFG), Byte Order Test Register bit of the Reset Control bit of the Reset Control Port x PHY Basic Control Register Port 2 PHY Reset SMSC LAN9303/LAN9303i ...
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... EEPROM Loader, while hard-straps cannot. Configuration straps which have a corresponding external pin include internal resistors in order to prevent the signal from floating when unconnected particular configuration strap is connected to SMSC LAN9303/LAN9303i Section 7.2.9, "PHY Power-Down Modes," on page 100 or the Reset (PHY_RST) until it clears ...
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... Section 8.4, "EEPROM Loader," on page 113 Table 4.2 means the register bit is loaded with the strap value, while the bit in the Reset Control Register (RESET_CTL) EEPROM Command Register 46 DATASHEET Datasheet 351. Chapter 3, "Pin Description and for information on or upon (E2P_CMD), these straps return SMSC LAN9303/LAN9303i ...
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... Control Register (PHY_BASIC_CONTROL_x) 10BASE-T Full Duplex the (PHY_AN_ADV_x) PHY Mode (MODE[2:0]) Modes Register (PHY_SPECIAL_MODES_x) Refer to the respective register definition sections for additional information. SMSC LAN9303/LAN9303i bits of the (LED_CFG). bits of the (LED_CFG). AMDIX_EN Strap State Port 1 (HW_CFG). to configure Port 1 Auto-MDIX Auto-MDIX Control (AMDIXCTRL) ...
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... Port x PHY Auto- Port 1 Backpressure Enable bit of the Port 1 Manual Flow Control Register and Port 1 Full-Duplex Receive Flow Control bits of the Port 1 Manual Flow Control bit of the Port x PHY Auto-Negotiation 48 DATASHEET Datasheet PIN / DEFAULT VALUE 1b bit of the bits SMSC LAN9303/LAN9303i ...
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... Control Register (PHY_BASIC_CONTROL_x) 10BASE-T Full Duplex the (PHY_AN_ADV_x) PHY Mode (MODE[2:0]) Modes Register (PHY_SPECIAL_MODES_x) Refer to the respective register definition sections for additional information. SMSC LAN9303/LAN9303i Port 1 Full-Duplex Manual Flow Control bit in the Port 1 Manual Flow (MANUAL_FC_1). and Symmetric Pause AMDIX_EN Strap State Port 2 (HW_CFG) ...
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... Port x PHY Special Port 2 Backpressure Enable bit of the Port 2 Manual Flow Control Register and Port 2 Full-Duplex Receive Flow Control bits of the Port 2 Manual Flow Control . bit of the Port x PHY Auto-Negotiation 50 DATASHEET Datasheet PIN / DEFAULT VALUE 1b bit of the bit SMSC LAN9303/LAN9303i ...
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... Control Enable (RX_FC_0) Control Register This strap affects the default value of the following register bits: Asymmetric Pause Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) SMSC LAN9303/LAN9303i Port 2 Full-Duplex Manual Flow Control bit in the Port 2 Manual Flow (MANUAL_FC_2). and Symmetric Pause (VPHY_AN_LP_BASE_ABILITY): Section 13 ...
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... MII PHY DESCRIPTION 2 C Managed Mode Section 2.3, "Modes of Operation," on page 19 Section 8.3, "I2C Master EEPROM 107. 52 DATASHEET Datasheet PIN / DEFAULT VALUE 0b bits of the 0b Table 4.3 provides a list of 23. PIN(S) MNGT1_LED4P : MNGT0_LED3P Note 4.1 for E2PSIZE_LED2P Note 4.1 SMSC LAN9303/LAN9303i ...
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... The LED is set as active high, since it is assumed that a LED to ground is used as the pull-down The LED is set as active low, since it is assumed that a LED to VDD is used as the pull-up. Note 4.1 This pin has shared strap functionality. Refer to SMSC LAN9303/LAN9303i DESCRIPTION P0_MODE[2:0] P0_mode_strap[1:0] 000 00 (MII MAC) ...
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... Port 2 PHY, and Port 1 PHY Interrupt Event (PHY_INT1) 57. Refer to for details on the operation and configuration of the PHY energy-detect 54 DATASHEET Datasheet STRAP NAME 2 led_pol_strap[5] led_pol_strap[4] led_pol_strap[3] led_pol_strap[2] led_pol_strap[1] led_pol_strap[0] Section 7.2.9.1, "PHY General Power- Port x PHY for Section 7.2.9.2, "PHY Energy Detect SMSC LAN9303/LAN9303i ...
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... IRQ output and is programmable via the (INT_DEAS) field of the de-assertion timer. The de-assertion interval starts when the IRQ pin de-asserts, regardless of the reason. SMSC LAN9303/LAN9303i (Buffer Manager, Switch Engine, and Port 2,1,0 MACs) (Port 1,2 PHYs) (GPT) (General Purpose) ...
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... SW_IPR register SWE_IPR Port [2,1,0] MAC Interrupt Registers MAC_[2,1,0] bits MAC_IMR_[2,1,0] of SW_IPR register MAC_IPR_[2,1,0] Port 2 PHY Interrupt Registers PHY_INTERRUPT_SOURCE_2 PHY_INTERRUPT_MASK_2 Port 1 PHY Interrupt Registers PHY_INTERRUPT_SOURCE_1 PHY_INTERRUPT_MASK_1 GPIO Interrupt Register GPIO_INT_STS_EN for bit-level definitions of all interrupt registers. 56 DATASHEET Datasheet BM_IMR BM_IPR SMSC LAN9303/LAN9303i ...
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... Port 2 PHYs are each capable of generating unique interrupts based on the following events: ENERGYON Activated Auto-Negotiation Complete Remote Fault Detected Link Down (Link Status Negated) SMSC LAN9303/LAN9303i Switch Fabric Interrupt Event (SWITCH_INT) (SW_IPR). (Port x MAC Interrupt Mask Register (MAC_IMR_x) for the Switch Engine, and/or ...
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... General Purpose Timer bit of the Interrupt IRQ Enable (IRQ_EN) 131. Interrupt Status Register (INT_STS) bit of the Interrupt Status bit of the Interrupt and Interrupt Interrupt Status Register (INT_STS) Device Ready must be set, and IRQ output must (IRQ_CFG). SMSC LAN9303/LAN9303i and ...
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... Status Registers," on page For detailed descriptions of all Switch Fabric related registers, refer to Descriptions," on page SMSC LAN9303/LAN9303i - These registers provide access to various Switch Fabric parameters for - A total of three MACs are included in the Switch Fabric which provide - This block is the core of the Switch Fabric and provides VLAN layer 2 ...
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... CSR for writing sequential register or Auto Decrement field written with the desired register Switch Fabric CSR Switch Fabric CSR Switch Fabric CSR Switch Fabric address range automatically set bits, clears the bit of the Switch Fabric CSR Interface address range SMSC LAN9303/LAN9303i ...
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... The user should clear the (AUTO_INC) and Auto Decrement (AUTO_DEC) unintended read cycle. Figure 6.2 illustrates the process required to perform a Switch Fabric CSR read. SMSC LAN9303/LAN9303i CSR Write Auto Increment / Decrement Idle Write Command ...
Page 62
... Register Register CSR_BUSY = 0 CSR_BUSY = 0 last data? Register Yes Write Command Register Read Data Register Table 6.1 details the Switch Fabric flow control enable logic. 62 DATASHEET Datasheet CSR_BUSY = 1 Read Data No Register (Port 1 Manual Flow Control Register (MANUAL_FC_2), or Port 0 Manual Flow SMSC LAN9303/LAN9303i ...
Page 63
... Advertisement Register (VPHY_AN_ADV) Base Page Ability Register "Virtual PHY Auto-Negotiation," on page 102 SMSC LAN9303/LAN9303i Port x PHY Auto-Negotiation Advertisement Register an d Virtual PHY egotia tio n Advertisement Register are not affected by the values of the manual flow control register. Refer to ...
Page 64
... Flow Control packet will be loaded into the pause counter. The pause function is enabled by either Auto-negotiation, or manually as discussed in Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 64 DATASHEET Datasheet Section 6.2.3, SMSC LAN9303/LAN9303i ...
Page 65
... Total alignment errors Total bytes received from all packets Total bytes received from good packets Total packets with a symbol error Total MAC control packets SMSC LAN9303/LAN9303i 62. Pause frames are consumed by the MAC and are not sent (MAC_RX_CFG_x). (Section 13.4.2.3, on page 229) (Section 13 ...
Page 66
... DATASHEET Datasheet TX Pad Enable bit of the Port x MAC Table 13.14, “Indirectly and Section 13.4.2.25 through 254) 255) 256) 257) 258) 259) 261) SMSC LAN9303/LAN9303i ...
Page 67
... Bit Age / Valid Static Filter Override SMSC LAN9303/LAN9303i (Section 13.4.2.37, on page 263) (Section 13.4.2.38, on page (Section 13.4.2.39, on page (Section 13.4.2.40, on page (Section 13.4.2.41, on page (Section 13.4.2.42, on page 268) Switch Engine ALR Write Data 0 Register and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) ...
Page 68
... Section 6.4.5, "Spanning Tree Support," on page and per entry with the Priority Enable bit, the transmit priority for MAC Switch Engine ALR Command Register (SWE_ALR_WR_DAT_0), and 68 DATASHEET Datasheet Switch Engine Port for additional (SWE_ALR_CMD_STS), Switch Switch Engine ALR Write Data 1 SMSC LAN9303/LAN9303i ...
Page 69
... Switch Engine ALR Command Register (SWE_ALR_CMD) Next Entry bit step 3. Note: Refer to Section 13.4.3.1, on page 271 definitions of these registers. SMSC LAN9303/LAN9303i with the desired MAC address and control Valid bit to 0. bit in the Switch Engine ALR Command Status Register until it is cleared. ...
Page 70
... VLAN broadcast domain containment resulted in zero valid destination ports, the packet is filtered. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII is in effect). for additional information effect). (This rule is for a destination MAC address 70 DATASHEET Datasheet SMSC LAN9303/LAN9303i ...
Page 71
... Source Port port default table programmable Priority 3b VLAN Priority Regeneration table per port 3b ALR Priority Figure 6.4 Switch Engine Transmit Queue Selection SMSC LAN9303/LAN9303i 3b priority 3b calculation static DA override 3b DA Highest Priority ALR Priority Enable Bit 71 DATASHEET Figure 6.4, the priority may ...
Page 72
... N DA Highest N Priority Y wait for ALR result ALR Priority Y Enable Bit Higher Priority Y Use Tag & Y Packet is Tagged N Y Packet is IPv4/v6 & Use IP N Use Tag & Y Packet is Tagged N Resolved Priority = Resolved Priority = Default Priority[Source Priority Regen[VLAN Port] Priority] SMSC LAN9303/LAN9303i ...
Page 73
... Priority Regeneration Table Register VLAN Priority Regeneration Table Register 2 Ingress VLAN Priority Regeneration Table Register Section 13.4.3.33, on page 308 these registers. SMSC LAN9303/LAN9303i Switch Engine VLAN Write Data Register (SWE_VLAN_RD_DATA), and Section 13.4.3.8, on page 280 for detailed VLAN register descriptions. Switch Engine DIFFSERV Table Command ...
Page 74
... Table 6.2 Spanning Tree States The host CPU may attempt to send packets to the port in this state, but they will not be transmitted. 74 DATASHEET Datasheet ... 11 0 VID for detailed VLAN (Section (Section 6.4.10, on page 80). is used to place a port into one of the Software Action SMSC LAN9303/LAN9303i ...
Page 75
... CBS. Once the Committed Burst bucket is full, the Excess Burst bucket is incremented up to the maximum set by the EBS. The CIR rate is specified in time per byte. The value programmed is in SMSC LAN9303/LAN9303i The MAC Address Table should be programmed with entries that the host CPU needs to receive (e ...
Page 76
... Section 13.4.3.29, on page 304 76 DATASHEET Datasheet Table 6.3. When a port is Bandwidth 100 Mbps 80 Mbps 67 Mbps 57 Mbps 50 Mbps 40 Mbps 31 Mbps 20 Mbps 10 Mbps 5 Mbps 2.5 Mbps 1 Mbps 500 Kbps 250 Kbps 100 Kbps 50 Kbps for detailed register SMSC LAN9303/LAN9303i ...
Page 77
... DIFFSERV Table 3b IPv 4 Precedence Programmable 2b Source Port Programmable Regeneration VLAN Priority Table per Port ALR Priority Figure 6.7 Switch Engine Ingress Flow Priority Selection SMSC LAN9303/LAN9303i Use IP 3b Priority 3b 3b Calculation Port Default Table DA Highest Priority ALR Priority Enable Bit Priority ...
Page 78
... N DA Highest N Priority Y wait for ALR result ALR Priority Enable Bit N VL Higher Priority Y Use Tag & Y Packet is Tagged N Packet is IPv4/v6 & Use IP N Use Tag & Y Packet is Tagged N Flow Priority = Flow Priority = Priority Regen[VLAN Port] Priority] SMSC LAN9303/LAN9303i ...
Page 79
... This function would be used if the monitoring port wished to participate in the IGMP group without the need to perform special handling in the transmit portion of the driver software. SMSC LAN9303/LAN9303i Switch Engine Broadcast Throttling Register 6.4. When a port is receiving at 10Mbps, any setting above 34 has the effect ...
Page 80
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII Switch Engine Port Mirroring Register are used to enable a special VLAN tag that and the port state for the CPU port is set to Forwarding or Learning). 80 DATASHEET Datasheet (SWE_PORT_MIRROR). and Buffer Manager configures the switch to SMSC LAN9303/LAN9303i ...
Page 81
... Upon egress from the host CPU port, the special tag is added regular VLAN tag already exists not deleted. Instead it will follow the special tag. SMSC LAN9303/LAN9303i is followed with the exception that is followed with the exception that the special tag is skipped ...
Page 82
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII Buffer Manager Drop Level Register Buffer Manager Broadcast Buffer Level Register Section 6.4.6, "Ingress Flow Metering and Coloring," Buffer Manager Configuration Register (BM_CFG) 82 DATASHEET Datasheet (BM_FC_PAUSE_LVL), and respectively. is set. If the Drop on is set, packets colored Yellow are SMSC LAN9303/LAN9303i ...
Page 83
... The value programmed is in approximately 20 nS per byte increments. Typical values are listed in Table 6.5. When a port is transmitting at 10 Mbps, any setting above 39 has the effect of not limiting the rate. SMSC LAN9303/LAN9303i (BM_RNDM_DSCRD_TBL_CMD), (BM_RNDM_DSCRD_TBL_WDATA), and (BM_RNDM_DSCRD_TBL_RDATA). The for additional details on writing and reading the ...
Page 84
... Mbps 80 Mbps 65 Mbps 67 Mbps 56 Mbps 57 Mbps 49 Mbps 50 Mbps 39 Mbps 40 Mbps 30 Mbps 31 Mbps 20 Mbps 20 Mbps 10 Mbps 10 Mbps 5 Mbps 5 Mbps 2.5 Mbps 2.5 Mbps 990 Kbps 1 Mbps 490 Kbps 500 Kbps 250 Kbps 250 Kbps 98 Kbps 100 Kbps 49 Kbps 50 Kbps 80. SMSC LAN9303/LAN9303i ...
Page 85
... The choice of ingress or egress is determined by the egress port’s VID / Priority Select bit. When a packet is received special-tagged from a CPU port, the special tag is removed. SMSC LAN9303/LAN9303i Buffer Manager Egress Port Type Register must be set. Second, the un-tag bit, for the egress port, from the un- (BM_EGRSS_PORT_TYPE) ...
Page 86
... VID / Priority Select bit Priority Select bit Change Priority Y N [egress_port] Modify Tag VID = Unchanged Priority = ingress priority or Send Packet Untouched Default Priority [egress_port]* *choosen by VID / Priority Select bit 86 DATASHEET Datasheet Special Tagged Strip Tag Strip Tag Strip Tag SMSC LAN9303/LAN9303i ...
Page 87
... Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) 6.6 Switch Fabric Interrupts The Switch Fabric is capable of generating multiple maskable interrupts from the Buffer Manager, Switch Engine, and MACs. These interrupts are detailed in on page 57. SMSC LAN9303/LAN9303i Section 5.2.1, "Switch Fabric Interrupts," 87 DATASHEET Revision 1.4 (07-07-10) ...
Page 88
... In addition, the Port 1 PHY and Port 2 PHY addresses can PHY Address (PHYADD) field in the PORT 1 PHY DEFAULT ADDRESS VALUE DATASHEET Datasheet for details on the Ethernet PHY phy_addr_sel_strap Port x PHY Special Modes Register Section 4.2.4, "Configuration Straps," on PORT 2 PHY DEFAULT ADDRESS VALUE SMSC LAN9303/LAN9303i ...
Page 89
... Negotiation MII MII To Port x MAC Switch Fabric MAC Interface PHY Management MDIO Control To MII Mux Registers Interrupts To System Interrupt Controller SMSC LAN9303/LAN9303i and 100BASE-TX Receive and 10BASE-T Receive 10/100 Transmitter HP Auto-MDIX 10/100 Reciever LEDs PLL To GPIO/LED From Controller System Clocks Controller Figure 7 ...
Page 90
... Shaded blocks are those which are 100M PLL MII MAC 4B/5B 25MHz Interface by 4 bits Encoder 125 Mbps Serial 100M MLT-3 MLT-3 TX Driver MLT-3 CAT-5 Section 7.2.7, "MII MAC 90 DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Magnetics Interface". Table 7.2. Each 4-bit data-nibble SMSC LAN9303/LAN9303i ...
Page 91
... MII Receive Data Valid (RXDV) 00000 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) 00001 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) SMSC LAN9303/LAN9303i Table 7.2 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 ...
Page 92
... MHz logic and the 100BASE-TX Transmitter. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII Table 7.2 4B/5B Code Table (continued) RECEIVER INTERPRETATION 92 DATASHEET Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID INVALID INVALID INVALID Section 7.1.1, "PHY SMSC LAN9303/LAN9303i ...
Page 93
... The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. SMSC LAN9303/LAN9303i Figure 7.3. Shaded blocks are those which are internal ...
Page 94
... Note: The PHY is connected to the Switch Fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 94 DATASHEET Datasheet Section 7.2.7, "MII MAC SMSC LAN9303/LAN9303i ...
Page 95
... The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice versa), then this is identified and corrected. The reversed condition is indicated by the 10Base-T Polarity State (XPOL) SMSC LAN9303/LAN9303i Section 7.2.7, "MII MAC in the Port x PHY Special Control/Status Indication ...
Page 96
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII Auto-Negotiation (PHY_AN) (PHY_BASIC_CONTROL_x). Port x PHY Auto-Negotiation Advertisement Section 13.3.2.5, "Port x PHY Auto-Negotiation 199. Refer to (PHY_AN_LP_BASE_ABILITY_x). 96 DATASHEET Datasheet Section 7.2.7, "MII MAC bit of the Section 4.2.4, "Configuration Port x PHY Special Control/Status Port x PHY Auto-Negotiation Link SMSC LAN9303/LAN9303i ...
Page 97
... PHY Pause Flow Control The Port 1 & 2 PHYs are capable of generating and receiving pause flow control frames per the IEEE 802.3 specification. The PHYs advertised pause flow control abilities are set via the SMSC LAN9303/LAN9303i Reset Control Register (RESET_CTL), or the (PHY_BASIC_CONTROL_x)) (Section 7.2.9, " ...
Page 98
... Full- Port 2 Full-Duplex Manual Flow Port x PHY Auto-Negotiation for additional information. bit in the is cleared to indicate that the link Parallel is set. Restart Auto-Negotiation (PHY_RST_AN) Restart Auto-Negotiation (PHY_BASIC_CONTROL_x), the device bit of the Port x PHY (Duplex Mode (PHY_BASIC_CONTROL_x). The speed should be SMSC LAN9303/LAN9303i ...
Page 99
... For a transmission, the Switch Fabric MAC drives the transmit data onto the internal MII TXD bus and asserts TXEN to indicate valid data. The data is in the form of 4-bit wide data at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T. SMSC LAN9303/LAN9303i Auto-MDIX Control (AMDIXCTRL) (PHY_SPECIAL_CONTROL_STAT_IND_x). When ...
Page 100
... Port 2 PHY Interrupt Event (PHY_INT2) Table 7.3 PHY Interrupt Sources PHY_INTERRUPT_MASK_x & PHY_INTERRUPT_SOURCE_x REGISTER BIT # 54. 100 DATASHEET Datasheet for a list of all supported Table 7.3. Reading shows the source of bits Port 1 PHY for the Port 1 and Port 2 Chapter 5, "System Interrupts," Section SMSC LAN9303/LAN9303i ...
Page 101
... After the PHY has returned from a power-down state, a reset of the PHY is automatically generated. The PHY power-down modes do not reload or reset the PHY registers. Refer to Power-Down Modes," on page 100 SMSC LAN9303/LAN9303i Power Down (PHY_PWR_DWN) (PHY_BASIC_CONTROL_x). In this mode the entire PHY, except the PHY Energy Detect Power-Down (EDPWRDOWN) (PHY_MODE_CONTROL_STATUS_x) ...
Page 102
... The magnetics selected for use with the device should be an Auto-MDIX style magnetic, which is widely available from several vendors. Please review the SMSC Application note 8.13 “Suggested Magnetics” for the latest qualified and suggested magnetics. A list of vendors and part numbers are provided within the application note ...
Page 103
... Virtual PHY Basic Control Register speed of operation to reflect the speed (Duplex Mode (VPHY_DUPLEX) The speed and duplex bits in the ignored when auto-negotiation is enabled. SMSC LAN9303/LAN9303i Parallel Detection is used. are dependant on the P0_DUPLEX pin and the Table 13.7 speed_strap_0 are set to indicate the emulated link partners abilities. ...
Page 104
... DATASHEET Datasheet and Asymmetric Pause bits of Section 13.2.6.5, "Virtual PHY Auto- 176. Symmetric Pause and Asymmetric (VPHY_AN_ADV). Thus, the Port 0 Manual Flow Control Register Virtual PHY Basic Control Register duplex_pol_strap_0 bit and controlling 42. by setting the Virtual PHY SMSC LAN9303/LAN9303i ...
Page 105
... Virtual PHY Software Reset via VPHY_BASIC_CTRL The Virtual PHY can also be reset by setting the Control Register (VPHY_BASIC_CTRL). This bit is self clearing and will return to 0 after the reset is complete. SMSC LAN9303/LAN9303i Reset (VPHY_RST) 105 DATASHEET bit of the Virtual PHY Basic ...
Page 106
... C-Bus Specification . 2 C master for accessing an external EEPROM and Master and the I C Slave Serial interfaces share common pins. The 106 DATASHEET Datasheet eeprom_size_strap 2 C-Bus Specification . 2 C slave serial interface (start and stop 2 C slave controller 2 C slave for control SMSC LAN9303/LAN9303i 2 C ...
Page 107
... The EEPROM controller drives all the address bits as requested regardless of the actual size of the EEPROM. The supported size ranges for I eeprom_size_strap # OF ADDRESS BYTES 0 1 Note 8.1 Bits in the control byte are used as the upper address bits. SMSC LAN9303/LAN9303i 2 C cycle. data data data can can ...
Page 108
... C EEPROM byte read for single and double byte addressing. Control Byte Chip / Block Select Bits 2 Figure 8 EEPROM Byte Read 111. 108 DATASHEET Datasheet Address High Address Low Byte Byte EEPROM Command Register Data Byte R/~W Double Byte Addressing Read Section 8.3.7, "I2C Master EEPROM SMSC LAN9303/LAN9303i bit ...
Page 109
... Once the I C master receives the acknowledge, it concludes by sending a start condition, followed by a stop condition, which will place the EEPROM into standby. SMSC LAN9303/LAN9303i bit in the 2 C master then sends an acknowledge, and the EEPROM responds with the 2 C EEPROM sequential byte reads for single and double byte addressing ...
Page 110
... EEPROM master runs at the standard mode rate. buf 2 C, this check is not performed (the bus is initially 110 DATASHEET Datasheet Conclude Poll Cycle Control Byte ... R/~W Chip / Block R/~W Select Bits Section 8.3.7, "I2C Master EEPROM bit in the EEPROM Command Register buf SMSC LAN9303/LAN9303i S P time ...
Page 111
... EEPROM Command Register (E2P_CMD) command is executed when the Command Register (E2P_CMD) EEPROM Controller Busy (EPC_BUSY) When issuing a READ command, the EEPROM Controller Address (EPC_ADDRESS) SMSC LAN9303/LAN9303i 2 C Master will return to the beginning of the Poll Section 8.3.6.4). bit in the EEPROM Command Register (E2P_CMD) (E2P_DATA). Section 8.4, " ...
Page 112
... Register Read E2P_CMD Register 112 DATASHEET Datasheet bit of the EEPROM Controller (E2P_CMD). The command bit of the EEPROM Command EEPROM Controller Busy (E2P_CMD). bit of the EEPROM Command EEPROM Read Idle Write E2P_CMD Register Read E2P_CMD Register EPC_BUSY = 0 Read E2P_DATA Register SMSC LAN9303/LAN9303i ...
Page 113
... EEPROM Command Register EEPROM Command Register (E2P_CMD) Ready (READY) bit of the device should be attempted. The operational flow of the EEPROM Loader can be seen in SMSC LAN9303/LAN9303i 2 C EEPROM controller, the PHYs, and to the system CSRs Reset Control Register (RESET_CTL)), or upon the issuance of a RELOAD (E2P_CMD) ...
Page 114
... Figure 8.7 EEPROM Loader Flow Diagram Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII Load PHY registers with N current straps Load PHY registers with N current straps N Y 114 DATASHEET Datasheet EPC_BUSY = 0 SMSC LAN9303/LAN9303i ...
Page 115
... Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) as detailed in Section 13.3.2.1, "Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)," on page 193. Additionally, the SMSC LAN9303/LAN9303i EEPROM Controller Busy (EPC_BUSY) (E2P_CMD). Otherwise, the EEPROM Loader will continue reading and Table 8.3. If the flag byte is not A5h, these next 4 bytes are skipped for more information on configuration straps ...
Page 116
... This can optionally generate an interrupt. 116 DATASHEET Datasheet Port x PHY Auto-Negotiation Virtual PHY Auto- is written with the new is written is written with the new defaults as bit is set in this register. This re-runs the Port 1 Manual Flow Control Register Port 0 Manual Flow SMSC LAN9303/LAN9303i 170. bit ...
Page 117
... I transmission and reception, and acknowledge generation and reception), handles the slave command protocol, and performs system register reads and writes. The C-Bus Specification . SMSC LAN9303/LAN9303i CSR Busy (CSR_BUSY) and the bit of the EEPROM Command Register (E2P_CMD) Section 8 ...
Page 118
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 2 C-Bus Specification for detailed I Figure 8.8. Address Byte R/~W 2 Figure 8 Slave Addressing Section 8.5.1, a register is read from the device when 118 DATASHEET Datasheet 2 C timing information Start or Stop or Data [31] SMSC LAN9303/LAN9303i ...
Page 119
... The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written (master sends a start stop condition occurs unexpectedly), the write is considered invalid and the SMSC LAN9303/LAN9303i Control Byte Data Byte ...
Page 120
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII C writes must not be performed to unused register addresses. Address Byte Data Byte Single Register Write ...Data m Byte Data 1 Byte .. . .. . Multiple Register Writes 2 Figure 8. Slave Writes 120 DATASHEET Datasheet Data Byte... ...Data Byte .. . Data m+1 Byte... ...Data n Byte .. . SMSC LAN9303/LAN9303i ...
Page 121
... MAC. At 0.6uS to 1.6uS (1.0uS nominal) following the de-assertion of P0_INDV, SQE_HEARTBEAT is set active for 0.5uS to 1.5uS ( bit times) (1.0uS nominal). This test is disabled via the Control/Status Register SMSC LAN9303/LAN9303i (VPHY_SPECIAL_CONTROL_STATUS). When set, this bit bit of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) ...
Page 122
... Virtual PHY is set. In this test mode, any Isolate bit of the Virtual PHY bit of the Virtual PHY Special is set. Transmissions from the Switch Isolate Virtual PHY Basic Control Register bit does not cause isolation of the MII bit of the Virtual PHY SMSC LAN9303/LAN9303i ...
Page 123
... Transmissions from the external MAC are ignored. An internal collision signal to the Switch Engine is available and is asserted when the loopback occurs regardless of the setting of the . SMSC LAN9303/LAN9303i RMII Clock Direction (VPHY_SPECIAL_CONTROL_STATUS), its drive strength is based on bit of the Virtual PHY Special Control/Status Register ...
Page 124
... Multiplexer. The SMI Slave inputs are set to 01b. A list of Section 2.3, "Modes of Table 10.1. The device Table 10.1. All addresses and data are TURN- AROUND TIME Note 10.2 DATA Z0 DDDDDDDDDDDDDDDD 1111110000000000 5432109876543210 10 DDDDDDDDDDDDDDDD 1111110000000000 5432109876543210 SMSC LAN9303/LAN9303i Datasheet SMI IDLE Note 10 ...
Page 125
... Note: In the event that a reset condition terminates between halves of 16-bit read pair, the device will not expect another 16-bit read to complete the DWORD cycle. Only specific registers may be read during a reset. Refer to SMSC LAN9303/LAN9303i should be polled. Once the correct pattern is can be polled to determine when the device initialization Section 4.2, " ...
Page 126
... Register Data burst sequence Section 8.4, "EEPROM Loader," on page 113 126 DATASHEET Datasheet Table 10.2. All addresses and data are TURN- TIME DATA Z0 DDDDDDDDDDDDDDDD 10 DDDDDDDDDDDDDDDD PHY Management for detailed information on these registers. and PHY Management for additional SMSC LAN9303/LAN9303i IDLE Note 10 Section ...
Page 127
... MDCLK PHY1 MDI MDO MDIO_ DIR MDCLK Management Mode Selection Figure 10.1 MII Mux Management Path Connections - MAC Mode SMI Managed SMSC LAN9303/LAN9303i and Section 8.4, "EEPROM Loader," on page 113 Management Mode Selection MDO MDCLK MDI MDO_EnN PMI Parallel Slave ...
Page 128
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 2 C Managed 2 C slave interface or the EEPROM Loader. for additional information. Management Mode Selection MDO MDCLK PMI Parallel Slave 128 DATASHEET Datasheet MII Pins MDIO_DIR MDO MDIO MDI MDC_DIR MDC_ OUT MDC MDC_IN MDI MDO_EnN 2 C Managed SMSC LAN9303/LAN9303i ...
Page 129
... MDCLK PHY1 MDI MDO MDIO_ DIR MDCLK Management Mode Selection Figure 10.3 MII Mux Management Path Connections - PHY Mode SMI Managed SMSC LAN9303/LAN9303i and Section 8.4, "EEPROM Loader," on page 113 Management Mode Selection MDO MDCLK MDI MDO_EnN PMI Parallel Slave ...
Page 130
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 2 C Managed Management Mode Selection MDO MDCLK PMI Parallel Slave 130 DATASHEET Datasheet 2 C slave interface or the EEPROM for additional information. MII Pins MDIO_DIR MDO MDIO MDI MDC_DIR MDC_ OUT MDC MDC_IN MDI MDO_EnN 2 C Managed SMSC LAN9303/LAN9303i ...
Page 131
... When the maximum count has been reached, the counter rolls over to zeros. The FRC does not generate interrupts. Note: The free running counter can take up to 160nS to clear after a reset event. SMSC LAN9303/LAN9303i field of the General Purpose Timer Configuration Register General Purpose Timer Enable (TIMER_EN) is asserted (1) ...
Page 132
... General Purpose I/O Configuration (GPIO_DATA_DIR). The GPIO Direction 5- (GPIO_DATA_DIR). When GPIO Buffer Type 5- (GPIO_CFG). Push/pull and bit in the General GPIO Data 5-0 (GPIOD[5:0]) General Purpose I/O Interrupt GPIO Interrupt[5:0] (GPIO[5:0]_INT) bit. The Chapter 5, "System Interrupts," on SMSC LAN9303/LAN9303i ...
Page 133
... Port 1 LED0 Speed (GPIO0) Port 1 The various LED indication functions shown in SMSC LAN9303/LAN9303i bits in the General Purpose I/O Configuration Register (GPIO_INT_STS_EN). When cleared, a low logic level on the LED Enable 5-0 (LED_EN[5:0]) (LED_CFG). These bits allow the configuration of each LED pin LED Function 1-0 (LED_FUN[1:0]) are determined by the Section 13.2.2.4, " ...
Page 134
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII is 00b, 01b, or 10b, the following LED rules apply: LED polarity hard-straps. LED polarity is determined by these hard-straps as is 00b, 01b, or 10b, the following LED function definitions 134 DATASHEET Datasheet 45. The LED polarity cannot be modified SMSC LAN9303/LAN9303i ...
Page 135
... Note: Link indication does not affect this function. RX_DV Port 2 - Non-stretched RX_DV signal from the PHY to the Switch Fabric. Note: Link indication does not affect this function. SMSC LAN9303/LAN9303i is 11b, the following LED rules apply: led_pol_strap[5:0] LED polarity hard-straps. The LED ...
Page 136
... Switch CSR Direct Data ... Registers 200h 1DCh Virtual PHY Registers 1C0h 1B0h Switch Interface Registers 1ACh 19Ch RESERVED 0ACh PHY Management Interface 0A8h 0A4h Registers 050h 04Ch RESERVED Base + 000h Figure 13.1 Base Register Memory Map 136 DATASHEET Datasheet SMSC LAN9303/LAN9303i ...
Page 137
... Many of these register bit notations can be combined. Some examples of this are shown below: R/W: Can be written. Will return current setting on a read. R/WAC: Will return current setting on a read. Writing anything clears the bit. SMSC LAN9303/LAN9303i Table 13.1 Register Bit Types REGISTER BIT DESCRIPTION ...
Page 138
... Section 13.2.5.1 PHY Management Interface Access Register, Section 13.2.5.2 Reserved for Future Use 138 DATASHEET Datasheet 2 C serial interface or the MIIM/SMI REGISTER NAME Section 13.2.7.1 Section 13.2.1.1 Section 13.2.1.2 Section 13.2.1.3 Section 13.2.7.2 Section 13.2.7.3 Section 13.2.7.5 Section 13.2.7.6 SMSC LAN9303/LAN9303i ...
Page 139
... RESET_CTL 1FCh RESERVED 200h-2DCh SWITCH_CSR_DIRECT_DATA 2E0h-3FFh RESERVED SMSC LAN9303/LAN9303i REGISTER NAME Port 1 Manual Flow Control Register, Port 2 Manual Flow Control Register, Port 0 Manual Flow Control Register, Switch Fabric CSR Interface Data Register, Section 13.2.4.4 Switch Fabric CSR Interface Command Register, Section 13 ...
Page 140
... Disable output on IRQ pin 1: Enable output on IRQ pin 7:5 RESERVED Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 55. 054h Size: DESCRIPTION 140 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 00h SMSC LAN9303/LAN9303i ...
Page 141
... When configured as an open-drain output, the IRQ_POL bit is ignored and the interrupt output is always active low. 0: IRQ pin open-drain output 1: IRQ pin push-pull driver Note 13.1 Register bits designated as NASR are not reset when the in the Reset Control Register (RESET_CTL) SMSC LAN9303/LAN9303i DESCRIPTION is set. 141 DATASHEET TYPE DEFAULT ...
Page 142
... Software Interrupt Enable Interrupt Enable Register (INT_EN) Switch Global Interrupt Pending Register Port x PHY Interrupt Source Port x PHY Interrupt Source General Purpose Timer Count Register General Purpose 142 DATASHEET Datasheet 32 bits Interrupt Enable Register (INT_EN). Where TYPE DEFAULT R/ set high SMSC LAN9303/LAN9303i ...
Page 143
... Port 1 PHY Interrupt Event Enable (PHY_INT1_EN) 25:20 RESERVED 19 GP Timer Interrupt Enable (GPT_INT_EN) 18:13 RESERVED 12 GPIO Interrupt Event Enable (GPIO_EN) 11:0 RESERVED SMSC LAN9303/LAN9303i 05Ch Size: Interrupt Status Register (INT_STS) Software Interrupt Enable Interrupt Status Register (INT_STS) DESCRIPTION 143 DATASHEET 32 bits register (SW_INT_EN)) ...
Page 144
... Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 1E0h Size: DESCRIPTION General Purpose (GPIO_INT_STS_EN). 144 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 0h SMSC LAN9303/LAN9303i ...
Page 145
... If the pin is an input, the data reflects the current state of the corresponding GPIO pin. If the pin is an output, the data is the value that was last written into this register. The pin direction is determined by the GPDIR bits of this register. SMSC LAN9303/LAN9303i 1E4h Size: DESCRIPTION ...
Page 146
... DESCRIPTION GPIO Interrupt bit of the Interrupt Enable Register General Purpose I/O Configuration 146 DATASHEET Datasheet 32 bits bit of the Interrupt Status Register bit of the TYPE DEFAULT R/WC 0h SMSC LAN9303/LAN9303i ...
Page 147
... Note 13.3 The default value of this field is determined by the configuration strap LED_en_strap[5:0]. Configuration strap values are latched on power-on reset or nRST de-assertion. Some configuration straps can be overridden by values from the EEPROM Loader. Refer to Section 4.2.4, "Configuration Straps," on page 45 SMSC LAN9303/LAN9303i 1BCh Size: DESCRIPTION 133 ...
Page 148
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII for additional information. 1B4h Size: DESCRIPTION (E2P_DATA). The E2P_CMD and EEPROM Controller Timeout for more information. 148 DATASHEET Datasheet Section 8.3, "I2C Master EEPROM 32 bits TYPE DEFAULT R SMSC LAN9303/LAN9303i ...
Page 149
... The bit is also set if the EEPROM fails to respond with the appropriate ACKs, if the EEPROM slave device holds the clock low for more than 30mS the I C bus is not acquired within 1.92 seconds unsupported EPC_COMMAND is attempted. This bit is cleared when written high. SMSC LAN9303/LAN9303i DESCRIPTION [28] Operation 0 READ 1 ...
Page 150
... This field is used by the EEPROM Controller to address a specific memory location in the serial EEPROM. This address must be byte aligned. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII DESCRIPTION Digital Reset (DIGITAL_RST) resets, or 150 DATASHEET Datasheet TYPE DEFAULT RO 0b R/W 0000h SMSC LAN9303/LAN9303i ...
Page 151
... This read/write register is used in conjunction with the perform read and write operations with the serial EEPROM. BITS 31:8 RESERVED 7:0 EEPROM Data (EEPROM_DATA) This field contains the data read from or written to the EEPROM. SMSC LAN9303/LAN9303i 1B8h Size: EEPROM Command Register (E2P_CMD) DESCRIPTION 151 DATASHEET 32 bits ...
Page 152
... Size: Section 6.2.3, "Flow Control Enable Logic," on page 62 DESCRIPTION 152 DATASHEET Datasheet Table 13.14. 59. For detailed 32 bits for additional Section 13.3.2.5, on page 199) TYPE DEFAULT RO - R/W Note 13.4 RO Note 13.5 RO Note 13.5 RO Note 13.5 R/W Note 13.6 SMSC LAN9303/LAN9303i ...
Page 153
... Note 13.7 The default value of this field is determined by the The strap values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the values, this register is updated with the new values. See SMSC LAN9303/LAN9303i DESCRIPTION for additional information. Section 4.2.4, "Configuration Straps," on page 45 ...
Page 154
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 1A4h Size: Section 6.2.3, "Flow Control Enable Logic," on page 62 DESCRIPTION 154 DATASHEET Datasheet 32 bits for additional Section 13.3.2.5, on page 199) TYPE DEFAULT RO - R/W Note 13.8 RO Note 13.9 RO Note 13.9 RO Note 13.9 R/W Note 13.10 R/W Note 13.10 SMSC LAN9303/LAN9303i ...
Page 155
... Note 13.11 The default value of this field is determined by the The strap values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the values, this register is updated with the new values. See SMSC LAN9303/LAN9303i DESCRIPTION for additional information. Section 4.2.4, "Configuration Straps," on page 45 ...
Page 156
... Section 6.2.3, "Flow Control Enable Logic," on page 62 Section 13.2.6.5, "Virtual PHY Auto-Negotiation Advertisement are not affected by the values of this register. DESCRIPTION 156 DATASHEET Datasheet 32 bits for additional TYPE DEFAULT RO - R/W Note 13.12 RO Note 13.13 RO Note 13.13 RO Note 13.13 R/W Note 13.14 R/W Note 13.14 SMSC LAN9303/LAN9303i ...
Page 157
... EEPROM Loader re-writes the value, this register is updated with the new values. In MAC mode, this bit is not re-written by the EEPROM Loader and has a default value of “1”. See Section 4.2.4, "Configuration Straps," on page 45 SMSC LAN9303/LAN9303i DESCRIPTION BP_EN_strap_0 for more information. ...
Page 158
... Switch Fabric CSR Interface Command Register to perform read and write operations with the Switch Fabric CSR’s. Refer to DESCRIPTION CSR Address (CSR_ADDR[15:0]) Read/Write (R_nW) (SWITCH_CSR_CMD). 158 DATASHEET Datasheet 32 bits for details on the registers TYPE DEFAULT R/W 00000000h bit in Read/Write SMSC LAN9303/LAN9303i ...
Page 159
... SWITCH_CSR_DATA register. 0: Disable Auto Decrement 1: Enable Auto Decrement 27:20 RESERVED SMSC LAN9303/LAN9303i 1B0h Size: Switch Fabric CSR Interface Data Register to control the read and write operations to the various Switch Fabric CSR’s. DESCRIPTION (SWITCH_CSR_DATA) ...
Page 160
... Accessible Switch Control and Status Registers,” on page 212 Switch Fabric CSR addresses. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII DESCRIPTION Table 13.14, “Indirectly for a list of 160 DATASHEET Datasheet TYPE DEFAULT R/W 0h R/W 00h SMSC LAN9303/LAN9303i ...
Page 161
... MAC Address for Port 0. 15:0 Physical Address[47:32] This field contains the upper 16-bits (47:32) of the physical address of the Switch Fabric MACs. Bits 41 and 10 are ignored if SMSC LAN9303/LAN9303i 1F0h Size DESCRIPTION DiffPauseAddr 161 ...
Page 162
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 1F4h Size for information on using the EEPROM Loader. DESCRIPTION Register Location Written SWITCH_MAC_ADDRL[7:0] SWITCH_MAC_ADDRL[15:8] SWITCH_MAC_ADDRL[23:16] SWITCH_MAC_ADDRL[31:24] SWITCH_MAC_ADDRH[7:0] SWITCH_MAC_ADDRH[15:8] 162 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W FF0F8000h Order of Reception on Ethernet SMSC LAN9303/LAN9303i ...
Page 163
... SWITCH_MAC_ADDRH 31 24 78h SWITCH_MAC_ADDRL Figure 13.2 Example SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Setup Note: By convention, the right nibble of the left most byte of the Ethernet address (in this example, the 2 of the 12h) is the most significant nibble and is transmitted/received first. SMSC LAN9303/LAN9303i BCh 9Ah ...
Page 164
... CSR CSR Busy (CSR_BUSY) bit is cleared. The address that is set is mapped via Section TYPE DEFAULT WO 00000000h Switch Fabric and Switch Fabric CSR Interface SWITCH_CSR_DIRECT_DATA ADDRESS 200h 204h 208h 20Ch 210h 214h 218h 21Ch 220h 224h SMSC LAN9303/LAN9303i ...
Page 165
... SWE_GLB_INGRESS_CFG SWE_PORT_INGRESS_CFG SWE_ADMT_ONLY_VLAN SWE_PORT_STATE SWE_PRI_TO_QUE SWE_PORT_MIRROR SWE_INGRESS_PORT_TYP SWE_BCST_THROT SWE_ADMT_N_MEMBER SWE_INGRESS_RATE_CFG SWE_INGRESS_RATE_CMD SWE_INGRESS_RATE_WR_DATA SWE_INGRESS_REGEN_TBL_0 SWE_INGRESS_REGEN_TBL_1 SWE_INGRESS_REGEN_TBL_2 SWE_IMR BM_CFG SMSC LAN9303/LAN9303i SWITCH FABRIC CSR REGISTER # Switch Port 2 CSRs 0C01h 0C40h 0C41h 0C80h Switch Engine CSRs 1800h 1801h 1802h 1809h 180Bh 180Ch 1811h 1812h ...
Page 166
... DATASHEET Datasheet SWITCH_CSR_DIRECT_DATA ADDRESS 29Ch 2A0h 2A4h 2A8h 2ACh 2B0h 2B4h 2B8h 2BCh 2C0h 2C4h 2C8h 2CCh 2D0h 2D4h 2D8h 2DCh SMSC LAN9303/LAN9303i ...
Page 167
... Upon a read, the value returned depends on the (MIIWnR) bit in the (PMI_ACCESS). If PHY. If MII Write (MIIWnR) written into this register. SMSC LAN9303/LAN9303i for additional information on the PHY registers. Refer 0A4h Size: PHY Management Interface Access Register DESCRIPTION MII Write PHY Management Interface Access Register ...
Page 168
... If this bit (PMI_DATA). PHY Management Interface or PHY Management Interface Access Register PHY Management Interface Data Register PHY Management Interface Data Register 168 DATASHEET Datasheet 32 bits PHY Management Interface Data TYPE DEFAULT RO - R/W 00000b R/W 00000b Section 13. R/W 0b PHY SMSC LAN9303/LAN9303i ...
Page 169
... VPHY_ID_LSB 4 VPHY_AN_ADV 5 VPHY_AN_LP_BASE_ABILITY 6 VPHY_AN_EXP 31 VPHY_SPEC_CTRL_STATUS SMSC LAN9303/LAN9303i Section 2.3, "Modes of Operation," on page 19 Table 13.5. For more information on the Virtual PHY access Section 13.3. For Virtual PHY functionality and operation information, see 102. REGISTER NAME Virtual PHY Basic Control Register, Virtual PHY Basic Status Register, ...
Page 170
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 1C0h Size: 0 Section 8.4, "EEPROM Loader," on page 113 DESCRIPTION bit is disabled. and Duplex Mode (VPHY_DUPLEX) (Note 13.18) 170 DATASHEET Datasheet 32 bits for more TYPE DEFAULT R/W 0b R/W 0b Auto- R/W 1b Speed Select bits R/W 0b R SMSC LAN9303/LAN9303i ...
Page 171
... Note 13.17 The reserved bits 31-16 are used to pad the register to 32-bits so that each register DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide. Note 13.18 The isolation does not apply to the MII management pins (MDIO). SMSC LAN9303/LAN9303i DESCRIPTION Auto-Negotiation (VPHY_AN) 171 ...
Page 172
... No extended status information in Register 15 1: Extended status information in Register 15 7 RESERVED Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 1C4h Size: 1 DESCRIPTION 172 DATASHEET Datasheet 32 bits TYPE DEFAULT Note 13. Note 13. Note 13. Note 13. SMSC LAN9303/LAN9303i ...
Page 173
... Note 13.23 The Virtual PHY never has remote faults, its link is always up, and does not detect jabber. Note 13.24 The VIrtual PHY supports basic and some extended register capability. The Virtual PHY supports Registers 0-6 (per the IEEE 802.3 specification). SMSC LAN9303/LAN9303i DESCRIPTION bit is first cleared on a reset, but set shortly after (when for additional details ...
Page 174
... Note 13.26 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 1C8h Size: 2 Virtual PHY Identification LSB Register DESCRIPTION (Note 13.26). 174 DATASHEET Datasheet 32 bits TYPE DEFAULT RO - R/W 0000h SMSC LAN9303/LAN9303i ...
Page 175
... Note 13.27 The reserved bits 31-16 are used to pad the register to 32-bits so that each register DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide. Note 13.28 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier. SMSC LAN9303/LAN9303i 1CCh Size: 3 ...
Page 176
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 1D0h Size: 4 Section 8.4, "EEPROM Loader," on page 113 DESCRIPTION 176 DATASHEET Datasheet 32 bits for more TYPE DEFAULT Note 13. Note 13. R/W Note 13.32 R/W Note 13. Note 13.33 R/W 1b R/W 1b R/W 1b SMSC LAN9303/LAN9303i ...
Page 177
... Configuration strap values are latched upon the de-assertion of a chip-level reset as described in Note 13.33 Virtual 100BASE-T4 is not supported. Note 13.34 The Virtual PHY supports only IEEE 802.3. Only a value of 00001b should be used in this field. SMSC LAN9303/LAN9303i DESCRIPTION bit is not useful since there is no actual link partner to send a fault to. and Asymmetric Pause bits default the strap is high (neither Symmetric and Asymmetric are advertised) ...
Page 178
... Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 1D4h Size: 5 DESCRIPTION 178 DATASHEET Datasheet 32 bits TYPE DEFAULT Note 13. Note 13. Note 13. Note 13.37 RO Note 13. Note 13.36 RO Note 13.38 SMSC LAN9303/LAN9303i ...
Page 179
... Asymmetric Pause 0 Towards Switch Asymmetric Pause 1 Towards MAC Symmetric Pause 1 SMSC LAN9303/LAN9303i DESCRIPTION and Symmetric Pause bits of the (VPHY_AN_ADV). Thus the emulated link partner always Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) configuration strap. This allows the user the choice of network emulation. ...
Page 180
... For more information on the Virtual PHY auto- Section 7.3.1, "Virtual PHY Auto-Negotiation," on page ADVERTISED LINK PARTNER ABILITY speed_strap_0 0 10BASE-T Full-Duplex (0010) 1 100BASE-X Full-Duplex (1000) 0 10BASE-T Half-Duplex (0001) 1 100BASE-X Half-Duplex (0100) 180 DATASHEET Datasheet Table 13.7 defines the Section 102. (BITS 8,7,6,5) SMSC LAN9303/LAN9303i ...
Page 181
... Note 13.42 The Page Received thereafter when the Auto-Negotiation process is run. Note 13.43 The emulated link partner will show Auto-Negotiation able unless Auto-Negotiation fails (no common bits between the advertised ability and the link partner ability). SMSC LAN9303/LAN9303i 1D8h Size: 6 DESCRIPTION bit is clear when read first cleared on reset, but set shortly ...
Page 182
... Port x MAC Receive Configuration Register Isolate (VPHY_ISO) bit of the RMII/Turbo MII Clock Strength 182 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 0b Virtual is set R/W Note 13.45 bit. RO Note 13.46 R/W 0b R/W Note 13.47 NASR Note 13.50 R/W Note 13.48 NASR Note 13.50 SMSC LAN9303/LAN9303i ...
Page 183
... Note 13.50 Register bits designated as NASR are reset when the Virtual PHY Reset is generated via the Reset Control Register (VPHY_BASIC_CTRL) Note 13.51 The default value of this field is determined via the configuration strap. Refer to additional information. SMSC LAN9303/LAN9303i DESCRIPTION [2] Speed 0 RESERVED 1 10Mbps 0 ...
Page 184
... This field indicates the design revision. Note 13.52 Default value is dependent on device revision. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 050h Size: DESCRIPTION 184 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 9303h RO Note 13.52 SMSC LAN9303/LAN9303i ...
Page 185
... Note: In SMI mode, either half of this register can be read without the need to read the other half. BITS 31:0 Byte Test (BYTE_TEST) This field reflects the current byte ordering SMSC LAN9303/LAN9303i 064h Size: DESCRIPTION 185 DATASHEET ...
Page 186
... Auto-MDIX Control (AMDIXCTRL) and 13.3.2.10). auto_mdix_strap_1 strap that connects to auto_mdix_strap_1 Auto-MDIX Control (AMDIXCTRL) and 13.3.2.10). 186 DATASHEET Datasheet 32 bits (Device Ready TYPE DEFAULT Note 13.53 Auto-MDIX RO Note 13.54 Auto-MDIX RO - for more information. for more information. SMSC LAN9303/LAN9303i ...
Page 187
... RESERVED 15:0 General Purpose Timer Pre-Load (GPT_LOAD) This value is pre-loaded into the GPT. This is the starting value of the GPT. The timer will begin decrementing from this value when enabled. SMSC LAN9303/LAN9303i 08Ch Size: (GPT_CNT). Refer to for additional information. DESCRIPTION 187 ...
Page 188
... Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 090h Size: General Purpose Timer Configuration Register (GPT_CFG) Section 11.1, "General Purpose Timer," on page 131 DESCRIPTION 188 DATASHEET Datasheet 32 bits to configure for additional TYPE DEFAULT FFFFh SMSC LAN9303/LAN9303i ...
Page 189
... When the maximum count has been reached, the counter will rollover to zero and continue counting. Note: The free running counter can take up to 160nS to clear after a reset event. SMSC LAN9303/LAN9303i 09Ch Size: for additional information. DESCRIPTION 189 ...
Page 190
... This bit is not accessible via the EEPROM Loader. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII 1F8h Size: DESCRIPTION should be polled to determine when 190 DATASHEET Datasheet 32 bits TYPE DEFAULT SMSC LAN9303/LAN9303i ...
Page 191
... PHY_ID_LSB_x 4 PHY_AN_ADV_x 5 PHY_AN_LP_BASE_ABILITY_x 6 PHY_AN_EXP_x SMSC LAN9303/LAN9303i 88. Section 13.2.6, "Virtual PHY," on page PHY Management Interface Access Register (PMI_ACCESS) registers (in MAC or PHY I Section 2.3, "Modes of Operation," on page 19 Section 7.1.1, "PHY Addressing," on page Port x PHY Basic Control Register, Port x PHY Basic Status Register, ...
Page 192
... Port x PHY Special Modes Register, Port x PHY Special Control/Status Indication Register, Section 13.3.2.10 Port x PHY Interrupt Source Flags Register, Port x PHY Interrupt Mask Register, Port x PHY Special Control/Status Register, 192 DATASHEET Datasheet Section 13.3.2.8 Section 13.3.2.9 Section 13.3.2.11 Section 13.3.2.12 Section 13.3.2.13 SMSC LAN9303/LAN9303i ...
Page 193
... Register (PHY_BASIC_STATUS_x) Note: The PHY_AN bit of this register must be cleared before setting this bit. 0: Normal operation 1: General power down mode 10 RESERVED SMSC LAN9303/LAN9303i Size: 16 bits Section 8.4, "EEPROM Loader," on page 113 DESCRIPTION bit in the Port x MAC Receive must be set for the ...
Page 194
... DATASHEET Datasheet TYPE DEFAULT R R/W Note 13.57 bit R for Port 2 PHY) and the Speed Select for Port 2 PHY). Essentially, if the (autoneg_strap_1 for Section 4.2.4, "Configuration autoneg_strap_2 for Port 2 PHY) and duplex_strap_2 for Port 2 PHY). Section 4.2.4, SMSC LAN9303/LAN9303i ...
Page 195
... This bit indicates the status of the Auto-Negotiation process. 0: Auto-Negotiation process not completed 1: Auto-Negotiation process completed 4 Remote Fault This bit indicates if a remote fault condition has been detected remote fault condition detected 1: Remote fault condition detected SMSC LAN9303/LAN9303i Size: 16 bits DESCRIPTION 195 DATASHEET TYPE DEFAULT ...
Page 196
... Note 13.58 The PHY supports 100BASE-TX (half and full duplex) and 10BASE-T (half and full duplex) only. All other modes will always return as 0 (unable to perform). Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII DESCRIPTION 196 DATASHEET Datasheet TYPE DEFAULT RO 1b RO/LL 0b RO/ SMSC LAN9303/LAN9303i ...
Page 197
... This read/write register contains the MSB of the Organizationally Unique Identifier (OUI) for the Port x PHY. The LSB of the PHY OUI is contained in the (PHY_ID_LSB_x). BITS 15:0 PHY ID This field is assigned to the 3rd through 18th bits of the OUI, respectively (OUI = 00800Fh). SMSC LAN9303/LAN9303i Size: 16 bits Port x PHY Identification LSB Register DESCRIPTION 197 DATASHEET TYPE ...
Page 198
... This field contain the 4-bit manufacturer’s revision number of the PHY. Revision 1.4 (07-07-10) Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII Size: 16 bits Port x PHY Identification MSB Register DESCRIPTION 198 DATASHEET Datasheet TYPE DEFAULT R/W 110000b R/W 001101b R/W 0001b SMSC LAN9303/LAN9303i ...
Page 199
... Half Duplex This bit determines the advertised 10BASE-T half duplex capability. 0: 10BASE-T half duplex ability not advertised 1: 10BASE-T half duplex ability advertised SMSC LAN9303/LAN9303i Size: 16 bits Section 8.4, "EEPROM Loader," on page 113 DESCRIPTION 199 DATASHEET for additional information ...
Page 200
... Port 2 PHY) with the logical for Port 1 PHY, speed_strap_2 for Port 1 PHY, duplex_strap_2 Section Section 4.2.4, "Configuration Straps," for Port 2 PHY) and the negated speed_strap_2 for Port 2 PHY). Section 4.2.4, "Configuration SMSC LAN9303/LAN9303i for for ...