EVB9303 SMSC, EVB9303 Datasheet - Page 21

• Manufacturer Part Number: EVB9303
• Description: EVALUATION BOARD FOR LAN9303
• Manufacturer: SMSC

Specifications of EVB9303

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9303
• Primary Attributes: 3 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: Full Duplex and HP Auto-MDIX Support, 10BASE-T and 100BASE-TX
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1095

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
MAC SMI
PHY SMI
MAC I
PHY I
MODE
2
2
C
C
internal Port 1&2 PHY registers or to all non-PHY registers (using addresses 16-31 and a non-standard
extended address map). MIIM and SMI use the same pins and protocol and differ only in that SMI
provides access to all internal registers while MIIM provides access to only the Port 1&2 PHY registers.
A special mode provides access to the Virtual PHY, which mimics the register operation of a single
port standalone PHY. This is used for software compatibility in managed operation.
The selection of management modes is determined at startup via the P0_MODE[2:0], MNGT1_LED4P,
and MNGT0_LED3P straps as detailed in
provided in
I
I
I
I
initial configuration from
initial configuration from
initial configuration from
initial configuration from
EEPROM and for CPU
EEPROM and for CPU
EEPROM and for CPU
EEPROM and for CPU
2
2
2
2
C master used to load
C master used to load
C master used to load
C master used to load
(MASTER/SLAVE)
I
I
I
2
2
2
C slave used for
C slave used for
R/W access to
R/W access to
R/W access to
R/W access to
Figure
C INTERFACE
management
management
EEPROM
EEPROM
EEPROM
EEPROM
2.4.
Table 2.1 Device Modes
used for CPU access
used for CPU access
used for CPU access
Virtual PHY, and non-
to internal PHYs and
Virtual PHY registers
DATASHEET
Virtual MIIM slave,
non-PHY registers
to internal PHYs,
used for external
SMI/MIIM slave,
to external PHY
SMI/MIIM slave,
MAC access to
PHY registers
MIIM master,
INTERFACE
SMI/MIIM
registers
Table
21
2.1. System configuration diagrams for each mode are
STRAP VALUE
P0_MODE[2:0]
or 110
or 110
001,
010,
100,
101,
001,
010,
100,
101,
011,
011,
000
000
MNGT0_LED3PST
Revision 1.4 (07-07-10)
MNGT1_LED4P,
RAP VALUE
01
10
01
10