EVB9303 SMSC, EVB9303 Datasheet - Page 20

• Manufacturer Part Number: EVB9303
• Description: EVALUATION BOARD FOR LAN9303
• Manufacturer: SMSC

Specifications of EVB9303

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9303
• Primary Attributes: 3 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: Full Duplex and HP Auto-MDIX Support, 10BASE-T and 100BASE-TX
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1095

Revision 1.4 (07-07-10)
2.3.3
2.3.4
PHY Mode
PHY mode utilizes an external MAC to provide a network path for the CPU. PHY mode supports MII
and RMII interfaces. The external MII/RMII pins must be connected to an external MAC, providing a
communication path to the Switch Fabric. MII PHY mode can operate at 10, 100, or 200Mbps (Turbo
mode). RMII PHY mode can operate at 10 or 100Mbps. In PHY mode, the device may be SMI
managed or I
When an EEPROM is connected, the EEPROM loader can be used to load the initial device
configuration from the external EEPROM via the I
can use the I
Management Modes
Various modes of management are provided in both MAC and PHY modes of operation. Two separate
interfaces may be used for management: the I
Interface Management) slave interface.
The I
external CPU. The I
The SMI/MIIM interface runs as either an SMI/MIIM slave or MIIM master. The master mode is used
to access an external PHYs registers under CPU control (assuming the CPU is using I
mode is used for register access by the CPU or external MAC and provides access to either the
2
C interface runs as an I
MII
LAN9303/
LAN9303i
MII
10/100
MAC
I
Ethernet
2
2
2
C EEPROM/
C interface to read or write the EEPROM.
C managed as detailed in
MIIM/
I
SMI
2
C slave
2
C slave and I
Magnetics
I
2
C
Figure 2.3 MII/RMII PHY Mode
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Figure 2.2 MII MAC Mode
EEPROM
2
(optional)
C slave. The slave mode is used as a register access path for an
2
DATASHEET
C master EEPROM interface are shared interfaces.
Section 2.3.4, "Management
MII
20
LAN9303/
LAN9303i
MII
10/100
PHY
I
2
C EEPROM/
RMII
MIIM/
I
SMI
2
2
2
C slave
C interface. Once operational, if managed, the CPU
RMII
C interface or the SMI/MIIM (Media Independent
LAN9303/
LAN9303i
10/100
MAC
I
2
C EEPROM/
MIIM/
I
SMI
2
C slave
I
2
C
EEPROM
(optional)
I
2
C
Modes".
EEPROM
(optional)
SMSC LAN9303/LAN9303i
2
C). The slave
Datasheet