IDT77V400S156DS IDT, Integrated Device Technology Inc, IDT77V400S156DS Datasheet - Page 8

• Manufacturer Part Number: IDT77V400S156DS
• Description: IC SW MEMORY 8X8 1.2BGPS 208PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156DS

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V400S156DS

A11-13, B11-13,
C12-13
A9-10, B9-10,C8-11 IFRM0-7
A3-8, A15-16, B3-8,
B14-16, C4-7,
C14-16, D14-16,
E14-16, F15-16
P10-12, R10-11,
T10-12
P7-9, R8-9, T7-9
K15, L14-16,M14-16,
N1-2, N14-16, P1-2,
P4-6, P15-16, R3-7,
R13-14, T3-6,T13-14
R12
A1
B2
P3, P14, R1-2, R15-
16, T1-2, T15-16
D4-13, E4-6, E11-13,
F4-5, F12-13, G4,
G13, H4, H13, J4,
J13, K4, K13, L4-5,
L12-13, M4-6, M11-
13, N4-13
E7-10, F6-11, G5-12,
H5-12, J5-12, K5-12,
L6-11, M7-10
Pin Number
IDT77V400
OCLK0-7
OP(0-7)D(0-3) O
ABYTE
SBYTE
NC
VCC
VSS
ICLK0-7
IP(0-7)D(0-3) I
OFRM0-7
CTLEN
Symbol
I
I
I
I/O
I
I
I
—
Power
Power
Type
Input Port Clock: Synchronizes the input data IPxD(0-3) and IFRMx signal associated with the input data port on the
positive clock edge. Each ICLKx is independent of the other seven ICLKs and SCLK. The ICLKs used are determined
by the configuration register initialization (see Port Configuration Code Table). The inputting of a cell may be halted by
stopping ICLKx.
Input Frame: Synchronous input registered on the rising edge of ICLKx. When asserted HIGH this signal denotes the
beginning of an input cell for the associated input port. IFRMs used are determined by the configuration register during
initialization (see Port Configuration Code Table).
Input Data: Eight 4-bit input ports. Synchronous with the rising edge of ICLK for the associated data port. IPxD(0-3)
can be assigned to different ICLKs and IFRMs via the configuration register during initialization. The ports may be
combined in groups to increase bandwidth by factors of 155Mbps (see Port Configuration Code Table). IPxD3 is the
MSb of the nibble. Example: IP0D3 is the MSb for port 0.
Output Clock: Synchronizes the output data OPxD(0-3) and OFRMx signal associated output data port on the positive
clock edge. Each OCLK is independent of the other seven OCLKs and SCLK. OCLKs used are determined by the port
configuration register during initialization (see Port Configuration Code Table). The transmission of a cell may be
halted by stopping oclkx.
Output Frame: Synchronous output on the rising edge of OCLK. The 77V400 marks the beginning of an output cell by
taking OFRM HIGH on the rising edge of OCLK. The output SAM nibble counter loads the start byte address from the
configuration register when a HIGH signal is sensed at the OFRM pin, thus re-synchronizing other chips connected to
the OFRM bus. OFRM is asserted HIGH one OCLK cycle prior to the first nibble of the cell being output from the
IDT77V400. OFRMs used are determined by the configuration register initialization (see Port Configuration Code
Table). During cell bus operations, the OFRM1-7 are redefined as CBUS1-7 for arbitration (there is no CBUS0).
Output Data: Eight 4-bit output ports. Synchronous with the rising edge of OCLK for the associated data port. OPxD(0-
3) can be assigned to different OCLKs and OFRMs via the configuration register. The 4 bit ports may be combined in
groups to increase the bandwidth by factors of 155Mbps (see Port Configuration Code Table). OPxD3 is the MSb of
the nibble. Example: IP0D3 is the MSb for port 0.
Control Enable: When asserted LOW, with OE LOW and the CTLEN bit set LOW in the configuration register, this pin
asynchronously enables all Control interface outputs. If CTLEN is HIGH all control interface outputs will be High-Z.
Add Byte to Input cell: Asynchronous DC signal. If an input port is in a 4-bit or 8-bit DPI mode and ABYTE is asserted
HIGH, a dummy byte will be inserted in the ninth byte position (after the HEC byte) to support systems requiring a byte
between the last header byte and the payload (otherwise ignored). Not intended for dynamic cycling or operation.
Subtract Byte to Output cell: Asynchronous DC signal. When and SBYTE is asserted HIGH, the dummy byte in the
ninth byte position (after the HEC byte) will be removed prior to transmission to support output port 4-bit and 8-bit DPI
modes (otherwise ignored). Not intended for dynamic cycling or operation.
No Connect
Power Supply (+3.3V +300mV)
Ground
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Description
March 31, 2001