IDT77V400S156DS IDT, Integrated Device Technology Inc, IDT77V400S156DS Datasheet - Page 17

• Manufacturer Part Number: IDT77V400S156DS
• Description: IC SW MEMORY 8X8 1.2BGPS 208PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156DS

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V400S156DS

CMD0-5
CMD0-5
IOD BUS
1
2
IOD0-31
IOD BUS
1
2
IOD0-31
1
2
IDT77V400
The Refresh sequence begins with the REF command and ends when the four cycle Buffer Memory Refresh has completed.
REFRESH command can only be valid for one cycle during a Refresh Sequence. Refresh must be completed prior to another command to avoid data corruption.
MODE
CS is Low
The 13-bit cell address and 4-bit selected Switching Memory address and 5-bits Edit Buffer Protect and Clear control bits are valid at this time.
MODE
The 13-bit cell address and 4-bit selected Switching Memory address are valid at this time.
CS is Low.
SCLK
SCLK
CMD0-5
IOD BUS
IOD0-31
MODE
SCLK
CS
STATUS
STATUS
GET
GET
Input
Output
Output
Figure 9 Multi-Sequence Functional Waveform Example - Idle, Memory Store, Initiate Memory Store
STATUS
Status
Status
GET
STATUS
Port
Port
GET
Input
Figure 10 Multi-Sequence Functional Waveform Example - Idle, Load, Initiate Load
Output
Output
REFRESH
GET HEADER
STATUS
GET
Status
Status
Port
Port
ISAM
2
Output
Output
Input
Figure 8 Functional Waveform - Refresh Sequence
Header
STATUS
STORE
Old
Status
OSAM
ISAM
LOAD
Port
GET
Output
Input
Input
PUT HEADER
OR HEADER
17 of 26
Address
Address
Status
Cell
Port
Cell
STATUS
GET
2
2
Input
Input
MEMORY STORE SEQUENCE n
Output
REFRESH SEQUENCE
STATUS
Header
STATUS
Header
GET
New
GET
Data
Status
Port
Output
Output
LOAD SEQUENCE n
STATUS
REFRESH CYCLE
Input
STATUS
GET
Status
GET
Port
Status
Port
MEMORY STORE CYCLE
1
Output
Output
LOAD CYCLE
STATUS
Status
Input
GET
OSAM
LOAD
Port
Status
Port
1
Output
Input
1
GET HEADER
OR HEADER
Status
ISAM
Address
Port
Cell
Input
STORE SEQUENCE n+1
March 31, 2001
Output
LOAD SEQUENCE n+1
2
3606 drw 14
Input
MEMORY
Header
Old
STORE
Header
ISAM
Data
3606 drw 15
3606 drw 16