IDT77V400S156DS IDT, Integrated Device Technology Inc, IDT77V400S156DS Datasheet - Page 12

• Manufacturer Part Number: IDT77V400S156DS
• Description: IC SW MEMORY 8X8 1.2BGPS 208PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156DS

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V400S156DS

Basic Functional Description
Basic Functional Description
Basic Functional Description
Basic Functional Description
data ports (IPxD). Each input port is configured as a double buffer with
SRAM storage for two complete ATM cells. Each input port also has an
independent input clock, (ICLK) and an input framing signal (IFRM).
the Control Data Bus (IOD Bus) to determine if any of the eight input
SAMs (ISAMx) are full and any of the eight Output SAMs (OSAMx) are
empty. The status register accessed through the IOD Bus also provides
ISAM error status information. If an error is detected for any of the
ISAMs, the error register can then be read through the IOD Bus to
further determine the presence of short or long cells or SAM overflow.
OFRM may also be used to monitor OSAM status.
to the cell memory at the location selected by the controller on the IOD
Bus. Similarly, on a Load command data from the specified cell memory
location is transferred to the OSAMx specified by the controller on the
IOD Bus. The output ports are also individually double buffered and
each output port can hold up to two complete ATM cells. A cell output
ready signals the status register to allow the loading of the second buffer
to begin while the first buffer begins to transmit via the 4-bit output port.
Each output port has an independent clock (OCLKx) and output framing
signal (OFRMx).
pre/post-pend bytes, if enabled, may be examined and modified via the
IOD bus. The CRC byte may also be modified, although it is modified
internally to the switching memory and is not read on the IOD Bus. The
IOD Bus is also used to set the internal configuration register at initial-
ization, determining the input and output cell length and the input and
output port configurations. The input edit buffer provides the means to
modify the cell header or pre/post-pend data of a cell in the ISAM before
storing the cell in the Memory portion of the IDT77V400. The command
selected (GHE or GPE, for example) will determine which bits are trans-
ferred to the control logic across the IOD bus. Two features are included
to eliminate the need for an extra step in the edit sequences of the input
edit buffer. A Byte Protect function, which prevents a PUT instruction
from changing any protected bytes stored in the input edit buffer, and a
Clear Byte function, which clears bytes in the input edit buffer in prepa-
ration for ORing at the output, are described in the Input Ports section of
this data sheet. See the Input and Output Edit Buffer Block Diagram for
additional details of the functionality and data path of this circuitry.
the last possible moment prior to transmission of a cell out an output
port. The output edit buffer provides data to an OR function between the
Buffer Memory and the OSAMs, allowing the IOD bus to set selected
bits in the cell header and pre/post pend data immediately before trans-
mission.
sections—the control interface, the input ports, and the output ports. For
clarity we will use an 8x8 Switching Memory configuration, with each
IDT77V400
Input data is received by the Switching Memory via the four-bit input
The external controller may poll the internal status register through
Upon a Store command, data from the selected ISAM is transferred
Once a cell has been received in the ISAM, the header bytes and the
The output edit buffer provides a means to modify the cell contents at
The following basic functional description is divided into three
12 of 26
port being 4-bits wide. Higher port bandwidth can be obtained by
combining multiple 4-bit wide ports into 8, 16, or 32-bit wide ports during
device initialization and configuration (see Configuration Codes Table).
Control Interface
Control Interface
Control Interface
Control Interface
(IOD0-31) is used to transfer address, data, and header information.
The 6-bit command bus (CMD0-5) is used when CS is LOW to issue
commands to the Switching Memory. When CS is HIGH, all issued
commands become invalid (no operation is performed) (see the Control
Interface Command Table for a listing of commands). The CRCERR
output pin indicates that a CRC error has occurred on the last header
when asserted LOW. The asynchronous OE input pin is the master
output enable for all outputs; all output drivers will be in a high-imped-
ance state when OE is driven HIGH. Upon power-up initialization the
OE pin should be held HIGH and the RESET pin should be asserted
HIGH to allow proper device initialization by the controller. The asyn-
chronous CTLEN input pin controls the Control Interface outputs. When
the CTLEN pin is LOW, the OE pin is LOW, and the CTLEN bit of the
configuration register is LOW, the Control Interface outputs are enabled.
If the CTLEN pin or the CTLEN bit of the configuration register is HIGH,
all control Interface outputs will be in the High-Z state (see Control
Enable Timing Waveform). The ADDR0-3 pins are used in conjunction
with the configuration register to selectively enable Switching Memories
that are sharing a control bus. All inputs and outputs of the control inter-
face, with the exception of OE, RESET, and ADDR0-3 are synchronous
with the system clock input (SCLK).
interface provides access to five internal registers — the configuration
register, the status register, the error register, the input edit buffers, and
the output edit buffers. The control interface is implemented as a pipe-
line. Commands are registered on the rising edge of SCLK, and in
general, the Switching Memory either expects data or will output data on
IOD0-31 on the subsequent SCLK rising edge. The Control Inter-face
Protocol Waveform shows an example of this protocol for the GHI (Get
Header from ISAMx) and GST (Get Status Register) instructions.
fully matched to the internal bandwidth of the Switching Memory, and to
the control requirements for high-speed multiport traffic. Additionally,
many of the commands which require multiple SCLK cycles to execute,
allow other commands to overlap the command cycles. In this manner,
the commands can be pipelined. The control interface of the Switching
Memory provides sufficient bandwidth to keep pace with the control
operations required of all sixteen data ports, the memory refresh activi-
ties, and the other associated overhead.
The control interface consists of 48 pins. The 32-bit control data bus
As shown in the Control Interface Timing Waveform, the control
The bus width and clock rate of the control interface has been care-
March 31, 2001