IDT77V400S156DS IDT, Integrated Device Technology Inc, IDT77V400S156DS Datasheet - Page 6

• Manufacturer Part Number: IDT77V400S156DS
• Description: IC SW MEMORY 8X8 1.2BGPS 208PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156DS

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V400S156DS

Pin Description - PQFP Package
Pin Description - PQFP Package
Pin Description - PQFP Package
Pin Description - PQFP Package
132
139
133-138
95
166
128-131
5-14, 17-27, 30-40
205
167-174
175-182
185-188, 160-163,
189-192, 150-153,
195-198, 146-149,
199-202, 142-145
86-93
74-81
45-48, 121-124, 57-
60, 115-118, 63-66,
109-112, 69-72, 97-
100
Pin Number
IDT77V400
SCLK
CS
CMD0-5
CRCERR
IFRM0-7
IP(0-7)D(0-3) I
OP(0-7)D(0-3) O
OE
RESET
ADDR0-3
IOD0-31
ICLK0-7
OCLK0-7
OFRM0-7
Symbol
I
I
I
I
I
I
I/O
O
I
I
I
I/O
Type
System clock: All bus control signals (CMD0-5, CS, IOD0-31, CRCERR) except OE are synchronous with respect to
SCLK. Control commands are registered on the positive edge of SCLK. The SCLK period must be less than or equal to
200ns during normal operation. Data Port signals are asynchronous with respect to SCLK.
Chip Select: Synchronous input which must be LOW at the rising edge of SCLK to enable the Command Bus CMD0-5.
Instructions are a NOP when CS is HIGH at the SCLK positive edge.
Command Bus: Synchronized to SCLK, instructions to be executed by the memory are transferred across this 6-bit
bus. CMD5 is the MSb of the Command Bus.
Output Enable: Asynchronous input that enables all outputs when asserted LOW. All outputs are High-Z when OE is
HIGH. IOD0-31 and CRCERR may also be set to High-Z by a HIGH CTLEN bit in the configuration register or a HIGH
CTLEN pin.
Reset: When asserted HIGH, the signal asynchronously allows the initialization of the registers and internal signals of
the IDT77V400. RESET should be asserted HIGH and OE should be held HIGH upon power-up for the external con-
troller to execute the initialization and insure proper system operation.
Chip Address: All ADDR inputs must OR the address in the configuration register bits 26-29 and then must match
1OD13-16 one cycle after the Store or Load command for selection to allow a Store or Load memory cycle to be exe-
cuted (full flag is cleared regardless of match, and empty must match before clear). ADDR3 is the MSb of the device
address bits.
Control Data Bus: Synchronous with SCLK. Used for external data transfer for the header pre/post-pend bytes, config-
uration register error and status registers, and the cell memory address. IOD31 is the MSb of the Control Data Bus.
Cyclical Redundancy Check Error: Synchronous output on the rising edge of SCLK. CRCERR asserted LOW after a
Header with CRC operation indicates that a CRC error has occurred on the previous header.
Input Port Clock: Synchronizes the input data IPxD(0-3) and IFRMx signal associated with the input data port on the
positive clock edge. Each ICLKx is independent of the other seven ICLKs and SCLK. The ICLKs used are determined
by the configuration register initialization (see Port Configuration Code Table). The inputting of a cell may be halted by
stopping ICLKx.
Input Frame: Synchronous input registered on the rising edge of ICLKx. When asserted HIGH this signal denotes the
beginning of an input cell for the associated input port. IFRMs used are determined by the configuration register during
initialization (see Port Configuration Code Table).
Input Data: Eight 4-bit input ports. Synchronous with the rising edge of ICLK for the associated data port. IPxD(0-3)
can be assigned to different ICLKs and IFRMs via the configuration register during initialization. The ports may be
combined in groups to increase bandwidth by factors of 155Mbps (see Port Configuration Code Table). IPxD3 is the
MSb of the nibble. Example: IP0D3 is the MSb for port 0.
Output Clock: Synchronizes the output data OPxD(0-3) and OFRMx signal associated output data port on the positive
clock edge. Each OCLK is independent of the other seven OCLKs and SCLK. OCLKs used are determined by the port
configuration register during initialization (see Port Configuration Code Table). The transmission of a cell may be
halted by stopping OCLKx.
Output Frame: Synchronous output on the rising edge of OCLK. The 77V400 marks the beginning of an output cell by
taking OFRM HIGH on the rising edge of OCLK. The output SAM nibble counter loads the start byte address from the
configuration register when a HIGH signal is sensed at the OFRM pin, thus re-synchronizing other chips connected to
the OFRM bus. OFRM is asserted HIGH one OCLK cycle prior to the first nibble of the cell being output from the
IDT77V400. OFRMs used are determined by the configuration register initialization (see Port Configuration Code
Table). During cell bus operations, the OFRM1-7 are redefined as CBUS1-7 for arbitration (there is no CBUS0).
Output Data: Eight 4-bit output ports. Synchronous with the rising edge of OCLK for the associated data port. OPxD(0-
3) can be assigned to different OCLKs and OFRMs via the configuration register. The 4 bit ports may be combined in
groups to increase the bandwidth by factors of 155Mbps (see Port Configuration Code Table). OPxD3 is the MSb of
the nibble. Example: IP0D3 is the MSb for port 0.
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Description
March 31, 2001