IDT77V400S156DS IDT, Integrated Device Technology Inc, IDT77V400S156DS Datasheet - Page 14

• Manufacturer Part Number: IDT77V400S156DS
• Description: IC SW MEMORY 8X8 1.2BGPS 208PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156DS

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V400S156DS

Control Enable Timing Waveform
Control Enable Timing Waveform
Control Enable Timing Waveform
Control Enable Timing Waveform
initialization the IOD bus will always be in input mode for multiple Switching Memory configurations.
Reset Waveform
Reset Waveform
Reset Waveform
Reset Waveform
command.
Input Port Timing Waveform
Input Port Timing Waveform
Input Port Timing Waveform
Input Port Timing Waveform
Output Port Timing Waveform
Output Port Timing Waveform
Output Port Timing Waveform
Output Port Timing Waveform
1
2
1ICLK frequency must not exceed the SCLK frequency.
2
1
IDT77V400
t
RESET must be Low 10ns prior to the next rising SCLK edge to insure that the Reset function is not repeated
t
OFRMx is actually tri-stated by the device one cycle before the end of the frame; the logic Low level is due to the recommended 5k ohm resistor on the OFRMx line.
The CTLEN bit of the configuration register (Bit 31) is LOW for this waveform. If the CTLEN bit of the configuration register is set HIGH at device
Reset function can also be accomplished by holding the RESET bit [Bit 30] High on the IOD bus during a LDC (Load Configuration Register)
RST
SIF
and t
must be greater than two SCLK cycles. Any glitch could cause an erroneous reset operation.
OPxD0-3
OFRMx
HIF
OCLKx
RESET
SCLK
IFRMx
IPxD0-3
(I
ICLKx
FRM
OE
IOD0-31
CTLEN
Setup and Hold) must be met for each I
1
2
OE
1
t
t
CDOF
CHO
t
CHI
t
OLZ
t
CYCO
t
t
CYCI
CYC
t
OE
t
CLO
t
CLI
t
SIF
t
t
CDOD
DCOF
t
HIF
Nibble 0
t
SID
CLK
Nibble 0
rising edge for I
t
t
t
DCOD
CTLZ
RST
t
HID
t
CTEN
1
Nibble 1
FRM
14 of 26
Low and High.
Nibble n-2
t
RSTL
2
Cell n
Cell n
ENABLED
Nibble n-1
1
(Last of cell)
Nibble n
(Last of cell)
Nibble n
t
CTHZ
Nibble 0
Nibble 0
t
Cell n+1
OHZ
3606 drw 08
Cell n+1
3606 drw 09
3606 drw 10
March 31, 2001
3606 drw 11