IDT77V400S156DS IDT, Integrated Device Technology Inc, IDT77V400S156DS Datasheet - Page 15

• Manufacturer Part Number: IDT77V400S156DS
• Description: IC SW MEMORY 8X8 1.2BGPS 208PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156DS

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V400S156DS

Input Ports
Input Ports
Input Ports
Input Ports
data bits (IPxD0-3), an input clock (ICLKx), and an input framing signal
(IFRMx). A further definition of the DPI interface is available in Technical
Note 34, available on the IDT Web Site (www.idt.com). The “x” in the
signal name corresponds to a port number (0 through 7 for the 8 x 8 port
configuration). IPxD0-3 and IFRMx are synchronous inputs with respect
to the rising edge of ICLKx, and the ICLK frequency must not exceed the
SCLK frequency. Each Input SAM (ISAMx) is double buffered, with each
ISAM buffer able to store a single ATM cell of up to 56 bytes in length.
The 32-bit Header and up to 32 bits of Pre-Pend and/or Post-Pend bytes
may be accessed and modified via the Control Data Bus interface.
Memory has been initialized and the ISAMs are empty. An active HIGH
IFRMx signal indicates that the first nibble of a new cell will be received
on the next rising edge of ICLKx and the cell counter is initialized. Data
will be sequentially clocked into the ISAM buffer on each subsequent
ICLKx rising edge after IFRMx goes LOW. The status register bit indi-
cating ISAMx buffer is full will be set HIGH when the ISAM counter
reaches the stop address. The ISAM start and stop address is
programmed via the configuration register at initialization to establish the
input cell length and protocol. If IFRMx input goes HIGH before the stop
position address is reached, the start byte position address will be
reloaded, the ISAM Full Status indicator will not be set, a Short Cell error
status indicator will be set in the error register, and the cells will be over-
written. If the IFRMx does not go HIGH when the stop position address
is reached, the ISAM Full status indicator and a Long Cell error status
indicator will be set. A Long Cell error results in the beginning portion of
the long cell being kept, the last portion being discarded, and the next
cell being accepted in the other half of the ISAM on the next IFRMx
HIGH. When the IFRMx input stays HIGH, the load start byte position
address process will repeat for every ICLKx and the actual count will not
start until IFRMx goes LOW. A subsequent cell may be input back-to-
back (no dead cycle on the IOD bus). In this case the IFRMx of the
second cell will occur on the same ICLKx rising edge as the last data
nibble of the first cell.
bus during a STORE command, the five most significant bits provide the
Byte Edit control for the first word of the input edit buffer. These four
bytes are either cleared, protected, or unaffected depending on the
value of the bits IOD27-31. These five bits are updated each time a
STORE command is executed. IOD31 determines if the function is clear
or protect; IOD 27-30 select which bytes in the first word of the Input edit
buffer are affected. The Edit Buffer Protect/Clear Codes table defines
the possible combination of these bits.
data; however, the ports can be combined in groups of four bits to
receive data rates up to 1.2Gbps. For example, four 4-bit ports can be
combined to receive 622Mbps traffic. The output ports can also be
combined, via the configuration register, independent of the input data
ports. This allows the Switching Memory to be configured as a concen-
trator, expander, or cell buffer with multiple bus widths. When combining
IDT77V400
A 155Mbps input Data Path Interface (DPI) consists of six pins – four
The Input Port Timing Waveform assumes that the Switching
When the control logic returns 32-bits of information across the IOD
Each of the eight 4-bit input ports is capable of receiving 155Mbps
15 of 26
ports, the chip is internally reconfigured to accept a single master ICLK
for the grouped ports (always using the least significant ICLK/IFRM of
those combined), and the data path is internally switched to correctly
align the ports for CRC generation and Header/Pre-Post Pend compar-
ison. See the Port Configuration Code Table for option definitions. By
varying the input and output port options, one hundred different port
configurations are available to the user to optimize design flexibility.
Output Ports
Output Ports
Output Ports
Output Ports
There are eight 155Mbps DPI ports, six pins each. Data is transmitted
out the 4-bit data bus (OPxD0-3), synchronous with the output clock
(OCLKx). An output framing signal (OFRMx) is provided which is also
synchronous with respect to OCLKx.
input port of another Switching Memory without requiring additional
logic. This allows cascading of multiple Switching Memory chips to
implement wider multiplexers or larger capacity cell buffers without addi-
tional logic. To facilitate cascading, OFRMx has been implemented as a
tri-statable I/O, while OPxD pins are tri-statable outputs. All chip outputs
can be disabled to a high impedance state by asserting the OE pin
HIGH.
output bus if they are configured in the cell bus mode, where control
logic performs the arbitration between IDT77V400s, or are externally
controlled via the OE. In the cell bus mode configuration, one external
controller would typically drive the control interface of multiple Switching
Memory chips and use the OFRMx to arbitrate the shared bus.
OSAMx) instruction from the external controller via the Command Bus to
dispatch a cell. The LDx instruction initiates a cell transfer from the
memory location specified on the IOD Bus to the specified OSAMx. At
this point the user has the option of modifying the Header and the Pre-
Post Pend bytes. When the output buffer has a cell loaded to send,
Switching Memory will immediately assert the specific OFRMx HIGH for
one OCLKx cycle prior to transmitting data. When the OFRMx is then
asserted LOW, the first data nibble of the new cell will appear prior to the
next rising edge of OCLKx. The output port will continue to assert
OFRMx LOW (while the cell is output from OSAMx) for a minimum of
two cycles before the end of the cell transmission. At that time (if in cell
bus mode) OFRMx is released to a high-impedance state during the
cycle before the end of the frame to allow collision free control transfer to
another Switching Memory. After asserting OFRMx HIGH, the OSAMx
EMPTY bit in the status register will be set, indicating that an OSAM
buffer is available for a new cell to be loaded from the memory. The
EMPTY bit is reset when a LDx command is performed and after the cell
is transmitted. It is recommended that a pull down resistor be used on
OFRMx pin to eliminate the possibility of an invalid OFRMx HIGH. The
value of this pull down resistor will be determined by a specific board
design or noise issues. A 5K
down function, although 50-100K
tions.
The output data ports are similar in operation to the input data ports.
The output port protocol was designed to interface directly with the
Output ports of a single device or of multiple devices may share an
Output SAM (OSAMx) control logic must receive a LDx (Load
resistor is recommended for this pull
may be sufficient in most applica-
March 31, 2001