IDT77V400S156DS IDT, Integrated Device Technology Inc, IDT77V400S156DS Datasheet - Page 2

• Manufacturer Part Number: IDT77V400S156DS
• Description: IC SW MEMORY 8X8 1.2BGPS 208PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V400S156DS

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V400S156DS

Description
Description
Description
Description
logic and memory necessary to perform high-speed buffering and
switching operations on ATM cell data. A single IDT77V400 provides a
cost effective switching element to implement an 8 x 8 155Mbps switch
with 1.2Gbps total switching bandwidth. The user configurable data
ports provide an aggregate bandwidth of 1.2Gbps for both receive and
transmit functions, and the cell lengths are user programmable to up to
56 bytes.
be as large as 56-bytes in length. The main cell memory is implemented
as a Buffer Memory array, and an on-chip cell address counter keeps
track of cell refresh requirements. There are also sixteen double-buff-
ered Serial Access Memories (SAM); eight for receiving and eight for
transmitting the ATM cells.
eight ports of 4-bits at 155Mbps each up to one 32-bit wide port at
1.2Gbps. The sixteen data ports are asynchronous with respect to each
other, and each port provides an independent data clock and cell
framing signal for start of cell indication. The SAMs are double-buffered
for each input and each output port to allow one cell to be transferred to
or from the internal memory while that data port continues to receive or
transmit a second cell. The cell framing and data clock signals imple-
ment a simple handshaking and synchronization protocol which allows
multiple Switching Memories to be connected to construct larger switch
arrays without requiring additional hardware.
Bus (CMD0-5), a 32-bit Control Data Bus (IOD0-31), a Chip Select pin
(CS), a 4-bit Address field (ADDR0-3), a RESET pin, an Output Enable
pin (OE), a Control Enable pin (CTLEN) and a CRCERR pin. All control
operations are synchronized with respect to the System Clock (SCLK),
with the exception of RESET, CTLEN, and OE, which are fully asynchro-
nous.
accessed through the Control Data Bus to define the cell length and the
input and output data port configurations. Internal error and status regis-
ters contain status information regarding each SAM and are accessible
via the Control Data Bus (IOD0-31). Input SAM full or Output SAM
empty status for all SAMs may be obtained in one access operation.
Additional information regarding the reception of short or long cells and
Input SAM overflow may also be obtained through the Control Data Bus.
storing cells in the shared memory, loading Output SAMs, polling the
status of the data ports, retrieving and storing original or modified
header bytes and pre-pend or post-pend bytes, and refreshing the cell
memory. Header CRC errors are indicated by a LOW CRCERR pin; the
CRC comparison byte may also be accessed via the status register,
which indicates the IPort on which the error was detected. A new CRC
can be generated upon storing a new header in the PHEC command.
Cell headers may be modified upon cell reception at the input ports or
IDT77V400
The IDT77V400 ATM Cell Based Switching Memory provides the
The memory provides storage for 8192 ATM cells, each of which can
The input data ports and output data ports are configurable from
The control interface of the IDT77V400 includes a 6-bit Command
The internal configuration register of the IDT77V400 can be
The command set of the Switching Memory provides functions for
2 of 26
upon cell transmit at the output ports. User defined pre-pend and post-
pend bytes may also be stored, retrieved, and modified through the
Control Data Bus.
variety of queuing disciplines. By maintaining the memory control in an
external controller, system level switching performance may be modified
over time as requirements change. In normal operation, the Switching
Memory port status is polled by the control function through the Control
Data Bus. Upon receiving a cell, the control function can retrieve the
header, check the CRC result, and store a new header if needed prior to
moving the cell to the shared memory. Pre-pended or post-pended
bytes may also be added or retrieved during this time. The output ports
are polled at the same time to determine when to send new cells to the
Output SAMs. The cell lengths of the input ports do not need to be the
same as the output port cell lengths, although all input ports and output
ports respectively must be configured to the same cell length.
details and implementation information.
an 208-pin Plastic Quad Flatpack (PQFP) and a 256-ball BGA.
The IDT77V400 has a generic control interface which supports a
Please refer to the SwichStar User Manual for additional feature
The IDT77V400 is fully 3.3V LVTTL compatible, and is packaged in
March 31, 2001