FAN6520AIMX Fairchild Semiconductor, FAN6520AIMX Datasheet - Page 8

• Manufacturer Part Number: FAN6520AIMX
• Description: IC CTRLR PWM SGL SYNC BUCK 8SOIC
• Manufacturer: Fairchild Semiconductor
• Type: Step-Down (Buck)r

Specifications of FAN6520AIMX

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 5.5 V
• Frequency - Switching: 300kHz
• Voltage - Input: 4.5 ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Power - Output: 715mW
• Topology: Boost, Buck
• Output Voltage: 0.8 V to 5.5 V
• Switching Frequency: 340 KHz
• Duty Cycle (max): 100 %
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Synchronous Pin: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

©2005 Fairchild Semiconductor Corporation
FAN6520A Rev. 1.0.5
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
error amplifier (Error Amp) output (V
with the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
V
output LC filter (L
The modulator transfer function is the small-signal trans-
fer function of V
by a DC gain and the output filter (L
a double-pole break frequency at F
F
(V
(ΔV
The following equations define the modulator break fre-
quencies as a function of the output LC filter:
ESR
IN
OUT
IN
OSC
at the SW node. The PWM wave is smoothed by the
) divided by the peak-to-peak oscillator voltage
F
F
. The DC gain of the modulator is the input voltage
) is regulated to the reference voltage level. The
ESR
LC
. )
=
Converter Compensation Design
=
COMP
------------------------ -
2π L C
COMP
Figure 7. Voltage Mode Buck
------------------------------------
2π
OSC
ERROR
AMP
DETAILED COMPENSATION
PWM
1
OUT
×
OUT
C1
ERROR
AMP
×
ESR
Z
1
/V
Z
COMPONENTS
FB
and C
FB
COMP
R2
FB
×
C2
C
0.8V
OUT
. This function is dominated
FB
+5V
0.8V
).
C3
V
IN
SW
Q2
R1
Z
OUT
R3
IN
L
LC
Z
C
OUT
E/A
IN
OUT
and C
and a zero at
) is compared
+V
OUT
OUT
V
OUT
), with
(3)
(4)
The compensation network consists of the error amplifier
(internal to the FAN6520A) and the impedance networks
Z
provide a closed-loop transfer function with the highest
0dB crossing frequency (F
gin. Phase margin is the difference between the closed-
loop phase at F
below relate the compensation network’s poles, zeros,
and gain to the components (R1, R2, R3, C1, C2, and
C3), shown in Figure 7.
Use the following steps to locate the poles and zeros of
the compensation network:
1.
2.
3.
4.
5.
6.
7.
Figure 8 shows an asymptotic plot of the DC-DC con-
verter’s gain vs. frequency. The actual modulator gain
has a high gain peak due to the high Q factor of the out-
put filter and is not shown in Figure 8. Using the above
guidelines should give a compensation gain similar to
the curve plotted. The open-loop error amplifier gain
bounds the compensation gain. Check the compensation
gain at FP2 with the capabilities of the error amplifier.
The closed-loop gain is constructed on the graph of Fig-
ure 8 by adding the modulator gain (in dB) to the com-
pensation gain (in dB). This is equivalent to multiplying
the modulator transfer function by the compensation
transfer function and plotting the gain.
The compensation gain uses external impedance net-
works Z
overall loop. A stable control loop has a gain crossing
with a –20dB/decade slope and a phase margin greater
than 45°. Include worst-case component variations when
determining phase margin.
IN
8
and Z
Pick gain (R2/R1) for the desired converter band-
width.
Place the first zero below the filter’s double pole
(~75% F
Place the second zero at filter’s double pole.
Place the first pole at the ESR zero.
Place the second pole at half the switching fre-
quency.
Check the gain against the error amplifier’s open-
loop gain.
Estimate phase margin. Repeat if necessary.
F
F
F
F
P1
P2
Z1
Z2
FB
FB
=
=
=
=
and Z
. The goal of the compensation network is to
--------------------- -
2πR
---------------------------------------- -
2πR
--------------------- -
2πR
--------------------------------------- -
2πC
LC
).
1
1
2
2
3
3
0dB
C
⎛
⎝
C
IN
(
R
--------------------
C
1
1
1
3
C
1
1
to provide a stable high bandwidth
and 180 degrees. The equations
1
+
+
C
C
R
2
3
2
0dB
⎞
⎠
)
) and adequate phase mar-
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(5)
(6)
(7)
(8)