MCZ33927EK Freescale Semiconductor, MCZ33927EK Datasheet - Page 29

• Manufacturer Part Number: MCZ33927EK
• Description: IC FET PRE-DRIVER 3PH 54-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33927EK

• Configuration: 3 Phase Bridge
• Input Type: Inverting and Non-Inverting
• Delay Time: 265ns
• Current - Peak: 600mA
• Number Of Configurations: 1
• Number Of Outputs: 3
• High Side Voltage - Max (bootstrap): 75V
• Voltage - Supply: 8 V ~ 40 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7. Command List
COMMAND DESCRIPTIONS
operating parameters, modes, and interrupt characteristics.
These commands are sent and status is read via 8-bit SPI
commands. The IC will use the last eight bits in a SPI transfer,
so devices can be daisy-chained. The first three bits in a SPI
FAULT REPORTING AND INTERRUPT
GENERATION
chapters can generate an interrupt - INT pin output signal
asserted high. When an interrupt occurs, the source can be
read from Status Register 0, which is also the return word of
most SPI messages.
faults are only cleared by sending the corresponding CLINTx
command. A fault that still exists will continue to assert an
interrupt.
will not toggle when one of the faults is cleared. Interrupt
processing circuitry on the host must be level sensitive to
correctly detect multiple simultaneous interrupt.
by sending a NULL command; the return word contains flags
Analog Integrated Circuit Device Data
Freescale Semiconductor
000x xxxx
0010 xxxx
0011 xxxx
010x xxxx
0110 xxxx
0111 xxxx
100x xxxx
Command
The IC contains internal registers to control the various
Different fault conditions described in the previous
Faults are latched on occurrence, and the interrupt and
Note: If there are multiple pending interrupts, the INT line
Thus, when an interrupt occurs, the host can query the IC
DEADTIME
MASK0
MASK1
CLINT0
CLINT1
Name
NULL
Mode
These commands are used to read IC status. These commands do not change any internal IC status. Returns
Status Register 0-3, depending on sub command.
Sets a portion of the interrupt mask using lower four bits of command. A “1” bit enables interrupt generation
for that flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0.
Sets a portion of the interrupt mask using lower four bits of command. A “1” bit enables interrupt generation
for that flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0.
Enables Desat/Phase Error Mode. Enables FULLON Mode. Locks further Mode changes. Returns Status
Register 0.
Clears a portion of the fault latch corresponding to MASK0 using lower four bits of command. A 1 bit clears
the interrupt latch for that flag. INT remains asserted if other unmasked faults are still present. Returns Status
Register 0.
Clears a portion of the fault latch corresponding to MASK1 using lower four bits of command. A 1 bit clears
the interrupt latch for that flag. INT remains asserted if other unmasked faults are still present. Returns Status
Register 0.
Set deadtime with calibration technique. Returns Status Register 0.
LOGIC COMMANDS AND REGISTERS
word can be considered to be the Command with the trailing
five bits being the data.
SPI message if the number of received bits is not eight or if it
is not a multiple of eight.
indicating any faults not cleared since the CLINTx command
was last written (rising edge of CS) and the beginning of the
current SPI command (falling edge of CS). The NULL
command causes no changes to the state of any of the fault
or mask bits.
1. A valid command had been received(i.e. no framing
2. A state change did not occur during the SPI message
The SPI logic will generate a framing error and ignore the
After RST, the first SPI result returned is Status Register 0.
The logic clearing the fault latches occurs only when:
error);
(if the bit is being returned as a 0 and a fault change
occurs during the middle of the SPI message, the latch
will remain set). The latch is cleared on the trailing
(rising) edge of the CS pulse. Note, to prevent missing
any faults the CLINTx command should not generally
clear any faults without being observed; i.e. it should
only clear faults returned in the prior NULL response.
Description
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
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