PCF8576DT/2,118 NXP Semiconductors, PCF8576DT/2,118 Datasheet - Page 24

• Manufacturer Part Number: PCF8576DT/2,118
• Description: IC LCD DRIVER 40/160SEG 56TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCF8576DT/2,118

• Package / Case: 56-TSSOP
• Display Type: LCD
• Configuration: 40 Segment
• Interface: I²C
• Current - Supply: 24µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 20
• Number Of Segments: 160
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4703 - DEMO BOARD LCD GRAPHIC DRIVER
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3558-2; 935276166118; PCF8576DT/2-T

NXP Semiconductors
PCF8576D
Product data sheet
The I
condition (S) from the I
slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I
ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level.
After an acknowledgement, one or more command bytes follow, that define the status of
each addressed PCF8576D.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C, (see
PCF8576D on the bus.
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data directed to the intended PCF8576D device.
An acknowledgement after each byte is asserted only by the PCF8576Ds that are
addressed via address lines A0, A1 and A2. After the last display byte, the I
asserts a STOP condition (P). Alternately a START may be asserted to restart an I
access.
Fig 17. I
Fig 18. Format of command byte
2
C-bus protocol is shown in
2
S
C-bus protocol
Figure
0 1 1 1 0 0
slave address
All information provided in this document is subject to legal disclaimers.
18). The command bytes are also acknowledged by all addressed
1 byte
Rev. 10 — 14 February 2011
2
C-bus master which is followed by one of two possible PCF8576D
S
A
0
R/W
MSB
0 A C
C
Figure
acknowledge by
all addressed
PCF8576Ds
n
COMMAND
≥ 1 byte(s)
REST OF OPCODE
17. The sequence is initiated with a START
Universal LCD driver for low multiplex rates
A
msa833
DISPLAY DATA
n
LSB
≥ 0 byte(s)
by A0, A1 and A2
update data pointers
subaddress counter
PCF8576D only
PCF8576D
and if necessary,
acknowledge
selected
2
C-bus transfer is
© NXP B.V. 2011. All rights reserved.
A
2
P
C-bus master
mdb078
2
C-bus
24 of 50