PCF8576DT/S400/2,1 NXP Semiconductors, PCF8576DT/S400/2,1 Datasheet
PCF8576DT/S400/2,1
Specifications of PCF8576DT/S400/2,1
Related parts for PCF8576DT/S400/2,1
PCF8576DT/S400/2,1 Summary of contents
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PCF8576D Universal LCD driver for low multiplex rates Rev. 13 — 10 May 2012 1. General description The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and ...
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... NXP Semiconductors May be cascaded for large LCD applications (up to 2560 elements possible) No external components required Compatible with chip-on-glass and chip-on-board technology Manufactured in silicon gate CMOS process 3. Ordering information Table 1. Ordering information Type number Package Name ...
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... NXP Semiconductors 5. Block diagram V LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR V DD SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF8576D PCF8576D Product data sheet Universal LCD driver for low multiplex rates BP0 BP2 BP1 BP3 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. PCF8576D Product data sheet 1 BP2 BP1 2 BP3 S10 14 PCF8576DT 15 S11 16 S12 S13 17 S14 18 S15 19 S16 20 21 S17 S18 22 S19 23 S20 24 S21 25 26 S22 27 S23 S24 28 Top view ...
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... NXP Semiconductors S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 Fig 3. PCF8576D Product data sheet Viewed from active side. C1 and C2 are alignment marks. For mechanical details, see ...
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... NXP Semiconductors 6.2 Pin description Table 3. Symbol SDA SCL CLK V DD SYNC OSC SA0 LCD BP0, BP2, BP1, BP3 S0 to S39 n.c. [1] The substrate (rear side of the die) is connected to V PCF8576D Product data sheet Pin description Pin PCF8576DT PCF8576DU 44 1, 58, 59 ...
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... NXP Semiconductors 7. Functional description The PCF8576D is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The possible display configurations of the PCF8576D depend on the number of active backplane outputs required ...
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... NXP Semiconductors Fig 5. The host microcontroller maintains the 2-line I PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin V appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies ...
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... NXP Semiconductors 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of ...
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... NXP Semiconductors V D ---------------------- - = V Using Equation 1 ⁄ bias ⁄ bias is 2 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • 1:3 multiplex ( • 1:4 multiplex ( These compare with It should be noted that V 7.3.1 Electro-optical performance Suitable values for V RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel ...
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... NXP Semiconductors Fig 6. PCF8576D Product data sheet 100 % OFF SEGMENT Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 13 — 10 May 2012 PCF8576D Universal LCD driver for low multiplex rates V [V] RMS V th(off) ...
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... NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment drive (S (1) V (2) V (3) V (4) V Fig 7. PCF8576D Product data sheet n V LCD BP0 LCD ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of Figure (1) V (2) V (3) V (4) V Fig 8. PCF8576D Product data sheet 9. V LCD BP0 LCD LCD ...
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... NXP Semiconductors (1) V (2) V (3) V (4) V Fig 9. PCF8576D Product data sheet V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD LCD LCD LCD S n LCD LCD LCD ...
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... NXP Semiconductors 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies (see Figure (1) V (2) V (3) V (4) V Fig 10. Waveforms for the 1:3 multiplex drive mode with PCF8576D Product data sheet 10). V LCD LCD BP0 LCD ...
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... NXP Semiconductors 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see Figure BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 (1) V (2) V (3) V (4) V Fig 11. Waveforms for the 1:4 multiplex drive mode with PCF8576D Product data sheet 11) ...
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... NXP Semiconductors 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF8576D and its LCD drive signals are timed either by its internal oscillator external clock. The internal oscillator is enabled by connecting pin OSC to pin V as the clock signal for several PCF8576Ds in the system that are connected in cascade. ...
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... NXP Semiconductors 7.9 Backplane outputs The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. • ...
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... NXP Semiconductors in pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment display showing all drive modes is given in depicted applies equally to other LCD types. The following applies to • In static drive mode the eight transmitted data bits are placed into row 0 as one byte. ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... NXP Semiconductors 7.10.1 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see an arriving data byte is stored at the display RAM address indicated by the data pointer ...
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... NXP Semiconductors If the bit at position BP2/S2 would be written by a second byte transmitted, then the mapping of the segment bits would change as illustrated in Table 7. Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display. Display RAM bits (rows)/ backplane outputs (BPn the case described in BP2/S8 etc ...
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... NXP Semiconductors mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.10.6 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration ...
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... NXP Semiconductors 7.12 Command decoder The command decoder identifies command bytes that arrive on the I commands available to the PCF8576D are defined in Table 9. Command Bit mode-set load-data-pointer device-select bank-select blink-select [1] Not used. All available commands carry a continuation bit C in their most significant bit position as shown in transfer to arrive will also represent a command ...
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... NXP Semiconductors Table 11. Bit [1] The possibility to disable the display allows implementation of blinking under external control. [2] Default value. [3] The display is disabled by setting all backplane and segment outputs to V [4] Not applicable for static drive mode. Table 12. See Section ...
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... NXP Semiconductors Table 14. See Section 7.10.5 Bit [1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. [2] Default value. Table 15. See Section Bit [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. [2] Default value. ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL Fig 16. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • ...
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... NXP Semiconductors 2 8.4 I C-bus controller The PCF8576D acts transmit data the acknowledge signals of the selected devices. Device selection depends on the 2 I C-bus slave address, on the transferred command data and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1, and A2 are ...
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... NXP Semiconductors Fig 18. I After an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF8576D. The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see PCF8576D on the bus. Fig 19. Format of command byte After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter ...
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... NXP Semiconductors 9. Internal circuitry Fig 20. Device protection circuits PCF8576D Product data sheet Universal LCD driver for low multiplex rates V DD SA0 CLK OSC SYNC A0 LCD BP0, BP1, BP2, BP3 V SS ...
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... NXP Semiconductors 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V display artifacts. To avoid such artifacts, V Table 17. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter LCD ...
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... NXP Semiconductors 11. Static characteristics Table 18. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD I LCD supply current DD(LCD) [3] Logic V power-on reset supply voltage P(POR) V LOW-level input voltage IL V HIGH-level input voltage ...
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... NXP Semiconductors 12. Dynamic characteristics Table 19. Dynamic characteristics Symbol Parameter Clock f internal clock frequency clk(int) f external clock frequency clk(ext) t HIGH-level clock time clk(H) t LOW-level clock time clk(L) Synchronization t SYNC propagation delay PD(SYNC_N) t SYNC LOW time SYNC_NL t driver propagation delay ...
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... NXP Semiconductors BP0 to BP3, and S0 to S39 Fig 21. Driver timing waveforms SDA SCL SDA Fig 22. I PCF8576D Product data sheet CLK t clk(H) CLK SYNC t PD(SYNC_N) t SYNC_NL t PD(drv BUF LOW t HD;STA C-bus timing waveforms All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 13. Application information 13.1 Cascaded operation In large display configurations PCF8576Ds can be differentiated on the same 2 I C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the programmable I Table 20. Cluster 1 2 PCF8576Ds connected in cascade are synchronized to allow the backplane signals from only one device in the cascade to be shared. This arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display ...
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... NXP Semiconductors The contact resistance between the SYNC on each cascaded device must be controlled. If the resistance is too high, the device is not able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 21 ...
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... NXP Semiconductors Fig 24. Synchronization of the cascade for the various PCF8576D drive modes 14. Test information The following quality information corresponds with the product type: PCF8576DT/S400/2 14.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications ...
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... NXP Semiconductors 15. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Bare die outline Wire bond die; 59 bonding pads 35 ( Notes 1. Marking code: PC8576D-2 Outline version IEC PCF8576DU/DA Fig 26. Bare die outline PCF8576DU/DA (for dimensions see PCF8576D Product data sheet Universal LCD driver for low multiplex rates D 22 ...
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... NXP Semiconductors Bare die; 59 bumps 35 ( Notes 1. Marking code: PC8576D-2 Outline version IEC PCF8576DU/2DA Fig 27. Bare die outline PCF8576DU/2DA (for dimensions see PCF8576D Product data sheet Universal LCD driver for low multiplex rates detail ...
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... NXP Semiconductors Table 22. Original dimensions are in mm. Unit (mm) max nom min [1] Dimension not drawn to scale. [2] Pad size. [3] Passivation opening. Table 23. Original dimensions are in mm. Unit (mm) max nom min [1] Dimension not drawn to scale. Table 24. All x/y coordinates represent the position of the center of each pad with respect to the center ...
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... NXP Semiconductors Table 24. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 ...
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... NXP Semiconductors Table 25. All x/y coordinates represent the position of the center of each alignment mark with respect to the center (x the chip (see Symbol C1 C2 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards ...
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... NXP Semiconductors Table 26. Symbol Fig 29. Tray alignment PCF8576D Product data sheet Tray dimensions (see Figure 28) Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction cut corner to pocket 1 ...
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... NXP Semiconductors 18.2 Carrier tape information Fig 30. Tape details Table 27. Symbol PCF8576D Product data sheet 4 pin 1 index W B0 direction of feed Carrier tape dimensions Description pocket width in x direction pocket width in y direction pocket height sprocket hole pitch tape width in y direction All information provided in this document is subject to legal disclaimers. Rev. 13 — ...
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... NXP Semiconductors 19. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 19.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 19.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 31. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 20. Abbreviations Table 30. Acronym CDM CMOS HBM ITO LCD LSB MM MSB MSL PCB RAM RMS SCL SDA ...
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... NXP Semiconductors 21. References [1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers [2] AN10365 — Surface mount reflow soldering description [3] AN10706 — Handling bare die [4] AN10853 — ESD and EMC sensitivity of IC [5] IEC 60134 — Rating systems for electronic tubes and valves and analogous ...
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... NXP Semiconductors 22. Revision history Table 31. Revision history Document ID Release date PCF8576D v.13 20120510 • Modifications: Fixed typos PCF8576D v.12 20120413 PCF8576D v.11 20110627 PCF8576D v.10 20110214 PCF8576D_9 20090825 PCF8576D_8 20090319 PCF8576D_7 20081218 PCF8576D_6 20081202 PCF8576D_5 20041222 PCF8576D_4 20041008 PCF8576D_3 20040617 PCF8576D_2 20030623 PCF8576D_1 20030401 PCF8576D ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die ...
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... NXP Semiconductors 25. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 4. Selection of possible display configurations . . . .7 Table 5. Biasing characteristics . . . . . . . . . . . . . . . . . . . .9 Table 6. Standard RAM filling in 1:3 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 7. Entire RAM filling by rewriting in 1:3 multiplex drive mode .22 [1] Table 8. Blinking frequencies Table 9. Definition of PCF8576D commands . . . . . . . .24 Table 10 ...
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... NXP Semiconductors 26. Figures Fig 1. Block diagram of PCF8576D . . . . . . . . . . . . . . . . .3 Fig 2. Pinning diagram for PCF8576DT (TSSOP56 Fig 3. Pinning diagram for PCF8576DU (bare die Fig 4. Example of displays suitable for PCF8576D . . . . .7 Fig 5. Typical system configuration . . . . . . . . . . . . . . . . .8 Fig 6. Electro-optical characteristic: relative transmission curve of the liquid . . . . . . . . . . . . . . 11 Fig 7. Static drive mode waveforms . . . . . . . . . . . . . . . .12 Fig 8 ...
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... NXP Semiconductors 27. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Power-On Reset (POR 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 8 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 9 7.3.1 Electro-optical performance . . . . . . . . . . . . . . 10 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . 12 7 ...