PCF8576DT/2,118 NXP Semiconductors, PCF8576DT/2,118 Datasheet

IC LCD DRIVER 40/160SEG 56TSSOP

PCF8576DT/2,118

Manufacturer Part Number
PCF8576DT/2,118
Description
IC LCD DRIVER 40/160SEG 56TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCF8576DT/2,118

Package / Case
56-TSSOP
Display Type
LCD
Configuration
40 Segment
Interface
I²C
Current - Supply
24µA
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Digits
20
Number Of Segments
160
Maximum Clock Frequency
400 KHz
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Power Dissipation
400 mW
Maximum Operating Temperature
+ 85 C
Maximum Supply Current
50 mA
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4703 - DEMO BOARD LCD GRAPHIC DRIVER
Digits Or Characters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-3558-2
935276166118
PCF8576DT/2-T
1. General description
2. Features and benefits
The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily
cascaded for larger LCD applications. The PCF8576D is compatible with most
microcontrollers and communicates via the two-line bidirectional I
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing and by display memory switching (static and duplex drive
modes).
PCF8576D
Universal LCD driver for low multiplex rates
Rev. 10 — 14 February 2011
AEC-Q100 compliant (PCF8576DT/S400/2) for automotive applications
Single chip LCD controller and driver
Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
Selectable display bias configuration: static,
Internal LCD bias generation with voltage-follower buffers
40 segment drives:
40 × 4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
Low power consumption
400 kHz I
May be cascaded for large LCD applications (up to 2560 elements possible)
No external components required
Compatible with chip-on-glass and chip-on-board technology
Manufactured in silicon gate CMOS process
Up to 20 7-segment numeric characters
Up to 10 14-segment alphanumeric characters
Any graphics of up to 160 elements
From 2.5 V for low-threshold LCDs
Up to 6.5 V for high-threshold twisted nematic LCDs
2
C-bus interface
1
2
or
1
3
2
C-bus. Communication
Product data sheet

Related parts for PCF8576DT/2,118

PCF8576DT/2,118 Summary of contents

Page 1

PCF8576D Universal LCD driver for low multiplex rates Rev. 10 — 14 February 2011 1. General description The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Type number PCF8576DT/2 PCF8576DT/S400/2 TSSOP56 PCF8576DU/DA/2 PCF8576DU/2DA/2 bare die [1] Chips in tray. [2] Chips with bumps in tray. 4. Marking Table 2. Type number PCF8576DT/2 PCF8576DT/S400/2 PCF8576DU/DA/2 PCF8576DU/2DA/2 PCF8576D Product data sheet Ordering information Package Name Description TSSOP56 plastic thin shrink small outline package, 56 leads ...

Page 3

... NXP Semiconductors 5. Block diagram V LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR V DD SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF8576D PCF8576D Product data sheet Universal LCD driver for low multiplex rates BP0 BP2 BP1 BP3 ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. PCF8576D Product data sheet BP2 1 BP1 2 BP3 S10 PCF8576DT 15 S11 S12 16 S13 17 S14 18 19 S15 20 S16 S17 21 S18 22 S19 23 24 S20 25 S21 S22 26 S23 27 S24 28 Top view. For mechanical details, see Pinning diagram for PCF8576DT/x (TSSOP56) All information provided in this document is subject to legal disclaimers. Rev. 10 — ...

Page 5

... NXP Semiconductors S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 Fig 3. PCF8576D Product data sheet Viewed from active side. C1 and C2 are alignment marks. For mechanical details, see and Figure 26. Pinning diagram for PCF8576DU/x (bare die) All information provided in this document is subject to legal disclaimers. Rev. 10 — ...

Page 6

... NXP Semiconductors 6.2 Pin description Table 3. Symbol SDA SCL CLK V DD SYNC OSC SA0 LCD BP0, BP2, BP1, BP3 S0 to S39 n.c. [1] The substrate (rear side of the die) is connected to V PCF8576D Product data sheet Pin description Pin PCF8576DT/x PCF8576DU All information provided in this document is subject to legal disclaimers. ...

Page 7

... NXP Semiconductors 7. Functional description The PCF8576D is a versatile peripheral device designed to interface any microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The possible display configurations of the PCF8576D depend on the number of active backplane outputs required ...

Page 8

... NXP Semiconductors • Input and output bank selectors are reset • The I • The data pointer and the subaddress counter are cleared (set to logic 0) • Display is disabled Data transfers on the I reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of ...

Page 9

... NXP Semiconductors where the values for n are for static mode for 1:2 multiplex for 1:3 multiplex for 1:4 multiplex The RMS off-state voltage ( off RMS Discrimination is the ratio ---------------------- - off RMS Using Equation ⁄ 1 bias is 2 ⁄ 1 bias is 2 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • ...

Page 10

... NXP Semiconductors V and V low manufacturer important to match the module properties to those of the driver in order to achieve optimum performance. Fig 5. PCF8576D Product data sheet are properties of the LCD liquid and can be provided by the module high 100 % OFF SEGMENT Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 10 — ...

Page 11

... NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment drive (S (1) V (2) V (3) V (4) V Fig 6. PCF8576D Product data sheet n V LCD BP0 ...

Page 12

... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of Figure 8. (1) V (2) V (3) V (4) V Fig 7. PCF8576D Product data sheet V LCD BP0 LCD V SS ...

Page 13

... NXP Semiconductors (1) V (2) V (3) V (4) V Fig 8. PCF8576D Product data sheet V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD LCD LCD LCD S n LCD LCD LCD LCD state − LCD − LCD −V LCD V LCD LCD LCD 0 V state 2 − ...

Page 14

... NXP Semiconductors 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies (see Figure (1) V (2) V (3) V (4) V Fig 9. PCF8576D Product data sheet 9). V LCD LCD BP0 LCD LCD LCD BP1 LCD V SS ...

Page 15

... NXP Semiconductors 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see Figure 10). BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 (1) V (2) V (3) V (4) V Fig 10. Waveforms for the 1:4 multiplex drive mode with ...

Page 16

... NXP Semiconductors 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF8576D and its LCD drive signals are timed either by its internal oscillator external clock. The internal oscillator is enabled by connecting pin OSC to pin V as the clock signal for several PCF8576Ds in the system that are connected in cascade. ...

Page 17

... NXP Semiconductors In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. ...

Page 18

LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...

Page 19

... NXP Semiconductors The following applies to • In the static drive mode, the eight transmitted data bits are placed in row 0 of eight successive 4-bit RAM words. • In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. ...

Page 20

... NXP Semiconductors The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8576D occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 14 display data byte transmitted in 1:3 multiplex mode) ...

Page 21

... NXP Semiconductors In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of LCD segments can blink selectively by changing the display RAM data at fixed time intervals. The entire display can blink at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 6 ...

Page 22

... NXP Semiconductors 7.16.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP ...

Page 23

... NXP Semiconductors • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I Fig 16 ...

Page 24

... NXP Semiconductors 2 The I C-bus protocol is shown in condition (S) from the I slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level. Fig 17. I After an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF8576D ...

Page 25

... NXP Semiconductors 7.17 Command decoder The command decoder identifies command bytes that arrive on the I The commands available to the PCF8576D are defined in Table 7. Command Bit mode-set load-data-pointer device-select bank-select blink-select [1] Not used. All available commands carry a continuation bit C in their most significant bit position as shown in arrive will also represent a command ...

Page 26

... NXP Semiconductors Table 10. Bit Table 11. Bit Table 12. Bit [1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. Table 13. Bit [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. [2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. ...

Page 27

... NXP Semiconductors 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the device’s status registers and coordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. ...

Page 28

... NXP Semiconductors 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 14. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter LCD DD(LCD tot ...

Page 29

... NXP Semiconductors 10. Static characteristics Table 15. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD I LCD supply current DD(LCD) Logic V power-on reset supply voltage P(POR) V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...

Page 30

... NXP Semiconductors 11. Dynamic characteristics Table 16. Dynamic characteristics Symbol Parameter Clock f internal clock frequency clk(int) f external clock frequency clk(ext) t HIGH-level clock time clk(H) t LOW-level clock time clk(L) Synchronization t SYNC propagation delay PD(SYNC_N) t SYNC LOW time SYNC_NL t driver propagation delay PD(drv) 2 [3] ...

Page 31

... NXP Semiconductors BP0 to BP3, and S0 to S39 Fig 20. Driver timing waveforms SDA SCL SDA Fig 21. I PCF8576D Product data sheet CLK t clk(H) CLK SYNC t PD(SYNC_N) t SYNC_NL t PD(drv BUF LOW t HD;STA C-bus timing waveforms All information provided in this document is subject to legal disclaimers. ...

Page 32

... NXP Semiconductors 12. Application information 12.1 Cascaded operation In large display configurations PCF8576Ds can be differentiated on the same 2 I C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the programmable I Table 17. Cluster 1 2 PCF8576Ds connected in cascade are synchronized to allow the backplane signals from only one device in the cascade to be shared. This arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display ...

Page 33

... NXP Semiconductors The contact resistance between the SYNC on each cascaded device must be controlled. If the resistance is too high, the device is not able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 18. ...

Page 34

... NXP Semiconductors Fig 23. Synchronization of the cascade for the various PCF8576D drive modes 13. Test information The following quality information corresponds with the following product type: PCF8576DT/S400/2 13.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications ...

Page 35

... NXP Semiconductors 14. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 36

... NXP Semiconductors 15. Bare die outline Wire bond die; 59 bonding pads 35 ( Notes 1. Marking code: PC8576D-2 Outline version IEC PCF8576DU/DA Fig 25. Bare die outline PCF8576DU/DA/2 (for dimensions see PCF8576D Product data sheet Universal LCD driver for low multiplex rates 0.5 scale References JEDEC ...

Page 37

... NXP Semiconductors Bare die; 59 bumps 35 ( Notes 1. Marking code: PC8576D-2 Outline version IEC PCF8576DU/2DA Fig 26. Bare die outline PCF8576DU/2DA/2 (for dimensions see PCF8576D Product data sheet Universal LCD driver for low multiplex rates detail X 0 0.5 scale References JEDEC JEITA Table All information provided in this document is subject to legal disclaimers. ...

Page 38

... NXP Semiconductors Table 19. Original dimensions are in mm. Unit (mm) max nom min [1] Dimension not drawn to scale. [2] Pad size. [3] Passivation opening. Table 20. Original dimensions are in mm. Unit (mm) max nom min [1] Dimension not drawn to scale. Table 21. All x/y coordinates represent the position of the center of each pad with respect to the center ...

Page 39

... NXP Semiconductors Table 21. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 ...

Page 40

... NXP Semiconductors Table 21. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol S39 SDA SDA Table 22. All x/y coordinates represent the position of the center of each alignment mark with respect to the center (x the chip (see ...

Page 41

... NXP Semiconductors Table 23. Symbol Fig 28. Tray alignment PCF8576D Product data sheet Tray dimensions (see Figure 27) Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction cut corner to pocket 1.1 center cut corner to pocket 1 ...

Page 42

... NXP Semiconductors 17.2 Carrier tape information Fig 29. Tape details Table 24. Symbol 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 43

... NXP Semiconductors • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0 ...

Page 44

... NXP Semiconductors Table 25. Package thickness (mm) < 2.5 ≥ 2.5 Table 26. Package thickness (mm) < 1.6 1.6 to 2.5 > 2.5 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “ ...

Page 45

... NXP Semiconductors 19. Abbreviations Table 27. Acronym CDM CMOS HBM ITO LCD LSB MM MSB MSL PCB RAM RMS SCL SDA SMD PCF8576D Product data sheet Abbreviations Description Charged-Device Model Complementary Metal-Oxide Semiconductor Human Body Model Indium Tin Oxide Liquid Crystal Display Least Significant Bit ...

Page 46

... NXP Semiconductors 20. References [1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers [2] AN10365 — Surface mount reflow soldering description [3] AN10706 — Handling bare die [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [5] IEC 61340-5 — ...

Page 47

... NXP Semiconductors 21. Revision history Table 28. Revision history Document ID Release date PCF8576D v.10 20110214 • Modifications: Adjusted die size • Removed product type PCF8576DH/2 • Adjusted values of I • Deleted power-on remark in PCF8576D_9 20090825 PCF8576D_8 20090319 PCF8576D_7 20081218 PCF8576D_6 20081202 PCF8576D_5 20041222 ...

Page 48

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 49

... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or 23 ...

Page 50

... NXP Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 8 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 8 7.3.1 Electro-optical performance . . . . . . . . . . . . . . . 9 7 ...

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