PCF8576DT NXP Semiconductors, PCF8576DT Datasheet
PCF8576DT
Specifications of PCF8576DT
Available stocks
Related parts for PCF8576DT
PCF8576DT Summary of contents
Page 1
... I C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). AEC-Q100 compliant (PCF8576DH/2 and PCF8576DT/S400/2) for automotive applications. 2. Features I Single chip LCD controller and driver I Selectable backplane drive confi ...
Page 2
... Marking codes Rev. 09 — 25 August 2009 PCF8576D Universal LCD driver for low multiplex rates [1] 2.01 0.38 mm [2] 2.01 0.40 mm Marking code PCF8576DH PCF8576DT PCF8576DT/S400 PC8576D-2 PC8576D-2 © NXP B.V. 2009. All rights reserved. Version SOT357-1 SOT364-1 SOT364-1 PCF8576DU/DA PCF8576DU/2DA ...
Page 3
... NXP Semiconductors 5. Block diagram V LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR V DD SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF8576D PCF8576D_9 Product data sheet Universal LCD driver for low multiplex rates BP0 BP2 BP1 BP3 ...
Page 4
... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. PCF8576D_9 Product data sheet n. S34 S35 3 S36 4 5 S37 S38 6 S39 7 n. n.c. SDA 10 SCL 11 12 SYNC 13 CLK OSC Top view. For mechanical details, see Figure Pinning diagram for PCF8576DH/2 (TQFP64) Rev. 09 — 25 August 2009 ...
Page 5
... S15 19 S16 20 21 S17 22 S18 S19 23 S20 24 25 S21 S22 26 S23 27 S24 28 Top view. For mechanical details, see Figure Pinning diagram for PCF8576DT/x (TSSOP56) Rev. 09 — 25 August 2009 PCF8576D Universal LCD driver for low multiplex rates 56 BP0 55 V LCD SA0 OSC ...
Page 6
... NXP Semiconductors S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 Fig 4. PCF8576D_9 Product data sheet PCF8576DU Top view. C1 and C2 are alignment marks. For mechanical details, see Pinning diagram for PCF8576DU/x (bare die) Rev. 09 — 25 August 2009 ...
Page 7
... The possible display configurations of the PCF8576D depend on the number of active backplane outputs required. A selection of display configurations is shown in of these configurations can be implemented in the typical system shown in Table 4. Number of: Backplanes Segments Digits PCF8576D_9 Product data sheet PCF8576DT/x PCF8576DU and and ...
Page 8
... NXP Semiconductors V V Fig 5. The host microprocessor or microcontroller maintains the 2-line I channel with the PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin V are generated internally. The only other connections required to complete the system are to the power supplies (V 7.1 Power-on reset At power-on the PCF8576D resets to the following starting conditions: • ...
Page 9
... NXP Semiconductors 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command (see that apply to the preferred modes of operation, together with the biasing characteristics as functions of V Table 5 ...
Page 10
... NXP Semiconductors ----------------------- - V off RMS Using Equation 1 bias bias is 2 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • 1:3 multiplex ( • 1:4 multiplex ( These compare with It should be noted that V PCF8576D_9 Product data sheet – ...
Page 11
... NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment drive (S (1) V (2) V (3) V (4) V Fig 6. PCF8576D_9 Product data sheet ) waveforms for this mode are shown in ...
Page 12
... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of Figure 8. (1) V (2) V (3) V (4) V Fig 7. PCF8576D_9 Product data sheet V LCD BP0 LCD V SS ...
Page 13
... NXP Semiconductors (1) V (2) V (3) V (4) V Fig 8. PCF8576D_9 Product data sheet V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD LCD LCD LCD S n LCD LCD LCD LCD state LCD LCD V LCD V LCD LCD LCD 0 V state LCD LCD V LCD ...
Page 14
... NXP Semiconductors 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies (see Figure (1) V (2) V (3) V (4) V Fig 9. PCF8576D_9 Product data sheet 9). V LCD LCD BP0 LCD LCD LCD BP1 LCD V SS ...
Page 15
... NXP Semiconductors 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see Figure 10). BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 (1) V (2) V (3) V (4) V Fig 10. Waveforms for the 1:4 multiplex drive mode with ...
Page 16
... NXP Semiconductors 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF8576D and its LCD drive signals are timed either by its internal oscillator external clock. The internal oscillator is enabled by connecting pin OSC to pin V as the clock signal for several PCF8576Ds in the system that are connected in cascade. ...
Page 17
... NXP Semiconductors In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. ...
Page 18
LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
Page 19
... NXP Semiconductors The following applies to • In the static drive mode, the eight transmitted data bits are placed in row 0 of eight successive 4-bit RAM words. • In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. ...
Page 20
... NXP Semiconductors The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8576D occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 14 display data byte transmitted in 1:3 multiplex mode) ...
Page 21
... NXP Semiconductors In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of LCD segments can blink selectively by changing the display RAM data at fixed time intervals. The entire display can blink at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 6 ...
Page 22
... NXP Semiconductors 7.16.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP ...
Page 23
... NXP Semiconductors • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I by transmitter Fig 16 ...
Page 24
... NXP Semiconductors 2 The I C-bus protocol is shown in condition (S) from the I slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level. Fig 17. I After an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF8576D. The last command byte sent is identifi ...
Page 25
... NXP Semiconductors 7.17 Command decoder The command decoder identifies command bytes that arrive on the I The commands available to the PCF8576D are defined in Table 7. Command Bit mode-set load-data-pointer device-select bank-select blink-select [1] Not used. All available commands carry a continuation bit C in their most significant bit position as shown in arrive will also represent a command ...
Page 26
... NXP Semiconductors Table 10. Bit Table 11. Bit Table 12. Bit [1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. Table 13. Bit [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. [2] Alternating RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. ...
Page 27
... NXP Semiconductors 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the device’s status registers and coordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. ...
Page 28
... NXP Semiconductors 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 14. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter LCD DD(LCD tot ...
Page 29
... NXP Semiconductors 10. Static characteristics Table 15. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD I LCD supply current DD(LCD) Logic V power-on reset supply voltage P(POR) V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...
Page 30
... NXP Semiconductors 11. Dynamic characteristics Table 16. Dynamic characteristics Symbol Parameter Clock f internal clock frequency clk(int) f external clock frequency clk(ext) t HIGH-level clock time clk(H) t LOW-level clock time clk(L) Synchronization t SYNC propagation delay PD(SYNC_N) t SYNC LOW time SYNC_NL t driver propagation delay PD(drv) 2 [3] ...
Page 31
... NXP Semiconductors BP0 to BP3, and S0 to S39 Fig 20. Driver timing waveforms SDA SCL SDA Fig 21. I PCF8576D_9 Product data sheet CLK t clk(H) CLK SYNC t PD(SYNC_N) t SYNC_NL t PD(drv BUF LOW t HD;STA C-bus timing waveforms Rev. 09 — 25 August 2009 PCF8576D Universal LCD driver for low multiplex rates ...
Page 32
... NXP Semiconductors 12. Application information 12.1 Cascaded operation In large display configurations PCF8576Ds can be differentiated on the same 2 I C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the programmable I Table 17. Cluster 1 2 PCF8576Ds connected in cascade are synchronized to allow the backplane signals from only one device in the cascade to be shared ...
Page 33
... NXP Semiconductors The contact resistance between the SYNC on each cascaded device must be controlled. If the resistance is too high, the device is not able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 18. ...
Page 34
... NXP Semiconductors Fig 23. Synchronization of the cascade for the various PCF8576D drive modes PCF8576D_9 Product data sheet Universal LCD driver for low multiplex rates BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode ...
Page 35
... NXP Semiconductors 13. Package outline TQFP64: plastic thin quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.05 1.2 mm 0.25 0.05 0.95 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC ...
Page 36
... NXP Semiconductors TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 37
... NXP Semiconductors 14. Bare die outline Wire bond die; 59 bonding pads; 2.26 x 2. Dimensions Unit max mm nom 0.38 2.26 2.01 min 0.072 Notes 1. Pad size 2. Passivation opening 3. Dimension not drawn to scale 4. Marking code: PC8576D-2 Outline version IEC PCF8576DU/DA Fig 26. Bare die outline PCF8576DU/DA/2 ...
Page 38
... NXP Semiconductors Bare die; 59 bumps; 2.26 x 2. Dimensions Unit max mm nom 0.40 0.015 0.381 0.052 min Notes 1. Dimension not drawn to scale 2. Marking code: PC8576D-2 Outline version IEC PCF8576DU/2DA Fig 27. Bare die outline PCF8576DU/2DA/2 PCF8576D_9 Product data sheet detail X 0 0.5 ...
Page 39
... NXP Semiconductors Table 19. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol SDA SCL SCL SYNC CLK V DD OSC SA0 LCD BP0 BP2 BP1 BP3 S10 S11 S12 S13 S14 S15 S16 ...
Page 40
... NXP Semiconductors Table 19. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 SDA SDA Table 20 ...
Page 41
... NXP Semiconductors 16. Packing information 16.1 Tray information Fig 28. Tray details Table 21. Symbol PCF8576D_9 Product data sheet 1,1 2,1 1,2 F 1,y Tray dimensions (see Figure 28) Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction ...
Page 42
... NXP Semiconductors Fig 29. Tray alignment 16.2 Carrier tape information Fig 30. Tape details Table 22. Symbol PCF8576D_9 Product data sheet 4 pin 1 index W B0 direction of feed Carrier tape dimensions Description pocket width in x direction pocket width in y direction pocket height sprocket hole pitch tape width in y direction Rev. 09 — ...
Page 43
... NXP Semiconductors 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
Page 44
... NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
Page 45
... NXP Semiconductors Fig 31. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Soldering of WLCSP packages 18.1 Introduction to soldering WLCSP packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note AN10439 “ ...
Page 46
... NXP Semiconductors • Solder paste printing issues, such as smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature), and cooling down imperative that the peak ...
Page 47
... NXP Semiconductors • The bump height on the chip The higher the stand off, the better the stresses are released due to TEC (Thermal Expansion Coefficient) differences between substrate and chip. 18.3.2 Quality of solder joint A flip-chip joint is considered good joint when the entire solder land has been wetted by the solder from the bump ...
Page 48
... NXP Semiconductors Table 26. Acronym RAM RMS SCL SDA SMD WLCSP PCF8576D_9 Product data sheet Abbreviations …continued Description Random Access Memory Root Mean Square Serial Clock Line Serial Data Line Surface Mount Device Wafer Level Chip-Size Package Rev. 09 — 25 August 2009 PCF8576D Universal LCD driver for low multiplex rates © ...
Page 49
... NXP Semiconductors 20. References [1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers [2] AN10365 — Surface mount reflow soldering description [3] AN10706 — Handling bare die [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [5] IEC 61340-5 — ...
Page 50
... NXP Semiconductors 21. Revision history Table 27. Revision history Document ID Release date PCF8576D_9 20090825 • Modifications: Added new type of PCF8576DT/S400/2 • Corrected LCD voltage equations PCF8576D_8 20090319 • Modifications: The typical value of the frame frequency has been corrected (see PCF8576D_7 20081218 • ...
Page 51
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 52
... NXP Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 LCD bias generator 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 9 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . 11 7 ...