EPC4QC100N Altera, EPC4QC100N Datasheet - Page 25

• Manufacturer Part Number: EPC4QC100N
• Description: IC CONFIG DEVICE 4MBIT 100-PQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC4QC100N

• Programmable Type: In System Programmable
• Memory Size: 4Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-MQFP, 100-PQFP
• Memory Type: Flash
• Clock Frequency: 66.7MHz
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: QFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C To +70°C
• Access Time: 90ns
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1378; EPC4QC100N

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Power-On Reset
Table 1–10. JTAG Interface Pins and Other Required Controller Pins (Part 2 of 2)
Power-On Reset
Power Sequencing
June 2011 Altera Corporation
EXCLK
PORSEL
TM0
TM1
Pin Name
1
The POR circuit keeps the system in reset until power-supply voltage levels have
stabilized. The POR time consists of the V
POR delay counter. When the supply is stable and the POR counter expires, the POR
circuit releases the OE pin. The POR time can be further extended by an external
device by driving the OE pin low.
Do not execute JTAG or ISP instructions until POR is complete.
The enhanced configuration device supports a programmable POR delay setting. You
can set the POR delay to the default 100-ms setting or reduce the POR delay to 2 ms
for systems that require fast power-up. The PORSEL input pin controls this POR delay;
a logic-high level selects the 2-ms delay, while a logic-low level selects the
100-ms delay.
The enhanced configuration device can enter reset under the following conditions:
■
■
■
Altera requires that you power-up the FPGA's V
configuration device's POR expires.
Pin Type
Input
Input
Input
Input
The POR reset starts at initial power-up during V
below the minimum operating condition anytime after V
The FPGA initiates reconfiguration by driving nSTATUS low, which occurs if the
FPGA detects a CRC error or if the FPGA’s nCONFIG input pin is asserted
The controller detects a configuration error and asserts OE to begin
re-configuration of the Altera FPGA (for example, when CONF_DONE stays low after
all configuration data has been transmitted)
Optional external clock input pin that can be used to generate the configuration
clock (DCLK).
When an external clock source is not used, connect this pin to a valid logic level
(high or low) to prevent a floating-input buffer. If EXCLK is used, toggling the
EXCLK input pin after the FPGA enters user mode will not effect the enhanced
configuration device operation.
This pin selects a 2-ms or 100-ms POR counter delay during power up. When
PORSEL is low, POR time is 100 ms. When PORSEL is high, POR time is 2 ms.
This pin must be connected to a valid logic level.
For normal operation, this test pin must be connected to GND.
For normal operating, this test pin must be connected to V
CC
ramp time and a user-programmable
Description
CCINT
CC
supply before the enhanced
ramp-up or if V
CC
Volume 2: Configuration Handbook
has stabilized
CC
.
CC
drops
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