EPC4QC100N Altera, EPC4QC100N Datasheet - Page 11

• Manufacturer Part Number: EPC4QC100N
• Description: IC CONFIG DEVICE 4MBIT 100-PQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC4QC100N

• Programmable Type: In System Programmable
• Memory Size: 4Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-MQFP, 100-PQFP
• Memory Type: Flash
• Clock Frequency: 66.7MHz
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: QFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C To +70°C
• Access Time: 90ns
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1378; EPC4QC100N

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Functional Description
June 2011 Altera Corporation
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After the first FPGA completes configuration, its nCEO pin asserts to activate the nCE
pin for the second FPGA, which prompts the second device to start capturing
configuration data. In this setup, the FPGAs CONF_DONE pins are tied together, and
hence all devices initialize and enter user mode simultaneously. If the enhanced
configuration device or one of the FPGAs detects an error, configuration stops (and
simultaneously restarts) for the whole chain because the nSTATUS pins are tied
together.
While Altera FPGAs can be cascaded in a configuration chain, the enhanced
configuration devices cannot be cascaded to configure larger devices or chains.
For configuration schematics and more information about multi-device FPP
configuration, refer to the appropriate FPGA family chapter in the
Handbook.
Passive Serial Configuration
APEX 20KC, APEX 20KE, APEX 20K, APEX II, Cyclone series, FLEX 10K, and Stratix
series devices can be configured using enhanced configuration devices in the PS
mode. This mode is similar to the FPP mode, with the exception that only one bit of
data (DATA[0]) is transmitted to the FPGA per DCLK cycle. The remaining DATA[7..1]
output pins are unused in this mode and drive low.
The configuration schematic for PS configuration of a single FPGA or single serial
chain is identical to the FPP schematic (with the exception that only DATA[0] output
from the enhanced configuration device connects to the FPGA DATA0 input pin;
remaining DATA[7..1] pins are left floating).
For configuration schematics and more information about multi-device PS
configuration, refer to the appropriate FPGA family chapter in the
Handbook.
Concurrent Configuration
Enhanced configuration devices support concurrent configuration of multiple FPGAs
(or FPGA chains) in PS mode. Concurrent configuration is when the enhanced
configuration device simultaneously outputs n bits of configuration data on the
DATA[n-1..0] pins (n = 1, 2, 4, or 8), and each DATA[] line serially configures a
different FPGA (chain). The number of concurrent serial chains is user-defined via the
Quartus II software and can be any number from 1 to 8. For example, three concurrent
chains you can select the 4-bit PS mode, and connect the least significant DATA bits to
the FPGAs or FPGA chains. Leave the most significant DATA bit (DATA[3])
unconnected. Similarly, for 5-, 6-, or 7-bit concurrent chains you can select the 8-bit PS
mode.
Figure 1–3
PS mode using an enhanced configuration device.
shows the schematic for configuring multiple FPGAs concurrently in the
Volume 2: Configuration Handbook
Configuration
Configuration
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