EPC4QC100N Altera, EPC4QC100N Datasheet

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... The flash memory is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete ...

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... FLEX 10K, FLEX 10KA, FLEX 10KE, Stratix, Stratix GX, Stratix II, Stratix GX, or Mercury device. Table 1–2. Configuration Devices Required (Part Family Arria GX Stratix Stratix GX Stratix II Stratix II GX June 2011 Altera Corporation Data Size (Bits) Device EPC4 (1) EP1AGX20C 9,640,672 EP1AGX35C 9,640,672 EP1AGX35D EP1AGX50C ...

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... EP20K100E 1,008,016 EP20K160E 1,524,016 EP20K200E 1,968,016 EP20K300E 2,741,616 EP20K400E 3,909,776 EP20K600E 5,673,936 EP20K1000E 8,960,016 EP20K1500E 12,042,256 EP2A15 4,358,512 EP2A25 6,275,200 EP2A40 9,640,528 EP2A70 17,417,088 Functional Description EPC16 (2) EPC8 (2) ( — — — — — — — — — 1 June 2011 Altera Corporation ...

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... Memory-Based EPC4, EPC8 and EPC16 Devices EPC devices support three different types of flash memory. supported flash memory for all EPC devices. Table 1–3. Enhanced Configuration Devices Flash Memory (Part Device EPC4 June 2011 Altera Corporation Data Size (Bits) Device (1) EPF10K10 118,000 ...

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... Source for EPC4, EPC8 and EPC16 Enhanced Configuration The external flash interface is currently supported in the EPC16 and EPC4 devices. For information about using this feature in the EPC8 device, contact Altera Applications at www.altera.com/support. Enhanced configuration devices have a 3.3-V core and I/O interface. The controller chip is a synchronous system that implements the various interfaces and features. Figure 1– ...

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... CONF_DONE lines. When the FPGA is ready (nSTATUS is high and CONF_DONE is low), the controller begins data transfer using the DCLK and DATA[] output pins. The controller selects the configuration page to be transmitted to the FPGA by sampling its PGM[2..0] pins after POR or reset. June 2011 Altera Corporation 1–7 Remote chapter in the Stratix Device ...

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... MHz). Hence, the flash read bandwidth is limited to about 160 megabits per second (Mbps) (16-bit flash data bus, DQ[], at 10 MHz). However, the configuration speeds supported by Altera FPGAs are much higher and translate to high configuration write bandwidths. For instance, 100-MHz Stratix FPP configuration requires data at the rate of 800 Mbps (8-bit DATA[] bus at 100 MHz) ...

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... Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Functional Description Configuration Signals Table 1–4 lists the configuration signal connections between the enhanced configuration device and Altera FPGAs. Table 1–4. Configuration Signals Enhanced Configuration Device Pin DATA[] DCLK nINIT_CONF, which ...

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... C-A1 (5) A1-F C-A15 (5) A15-F C-A16 (5) A16-F either directly or through a resistor. CC Table 1–10 supply from V . For more information, refer section CCW CC Functional Description N.C. N.C. N.C. N.C. N.C. V (7) CC (4) (4) (4) ® II software. To turn off the “Intel-Flash-Based EPC June 2011 Altera Corporation ...

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... FPGAs detects an error, configuration stops (and simultaneously restarts) for the whole chain because the nSTATUS pins are tied together. 1 While Altera FPGAs can be cascaded in a configuration chain, the enhanced configuration devices cannot be cascaded to configure larger devices or chains. f For configuration schematics and more information about multi-device FPP configuration, refer to the appropriate FPGA family chapter in the Handbook ...

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... CC Table 1–10 supply from V . For more information, refer section CCW CC Functional Description Device WE#F RP#F N.C. A[20..0] N.C. RY/BY# N.C. CE# N.C. OE# N.C. DQ[15..0] (3) V (7) CC VCCW (4) PORSEL (4) PGM[2..0] EXCLK (4) A0-F A1-F A15-F A16-F “Intel-Flash-Based EPC June 2011 Altera Corporation ...

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... Since the internal flash interface is directly connected to the external flash interface pins, controller flash access cycles will toggle the external flash interface pins. The external device must be able to tri-state its flash interface during these operations and ignore transitions on the flash interface pins. June 2011 Altera Corporation Mode (n =) (1) Used Outputs ...

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... For the Intel Advanced Boot Block Flash Memory (B3) 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Datasheet, visit www.intel.com. Volume 2: Configuration Handbook Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Altera Enhanced Configuration Devices Functional Description chapter in volume 2 of the June 2011 Altera Corporation ...

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... Figure 1–4: (1) For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications. (2) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should be left floating. These pins should not be connected to any signal; they are no-connect pins. ...

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... < V until V is fully powered up. PP PPLK powered up. PP < PPLK . CC should reach the minimum V CC Functional Description disables writes. PPLK is a programming PP is equivalent to the VCCW pin on PP before 50 ms and RP# CC June 2011 Altera Corporation ...

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... For detailed information about the page-mode feature implementation and programming file generation steps using the Quartus II software, refer to the Enhanced Configuration Devices June 2011 Altera Corporation in the Stratix Device Handbook. chapter in volume 2 of the Configuration Handbook. Volume 2: Configuration Handbook 1–17 ...

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... These unused routing and logic resources as well as un-initialized memory structures result in a large number of configuration RAM bits in the disabled state. Altera's proprietary compression algorithm takes advantage of such bitstream qualities. The general guideline for effectiveness of compression is the higher the device ...

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... MHz) The DCLK frequency is limited by the maximum DCLK frequency the FPGA supports. f The maximum DCLK input frequency supported by the FGPA is specified in the appropriate FPGA family chapter in the June 2011 Altera Corporation Table 1–6 lists sample compression ratios from a suite of (Note 1) Minimum 98% 1 ...

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... Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Table 1–7. Min (MHz) Typ (MHz) 6.4 8.0 21.0 26.5 32.0 40.0 42.0 53.0 Altera Enhanced Configuration Devices Functional Description Max (MHz) 10.0 33.0 50.0 66.0 chapter in volume 2 June 2011 Altera Corporation ...

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... If initial programming of the enhanced configuration device is done in-system via the external flash interface, the controller must be kept in reset by driving the FPGA nCONFIG line low to prevent contention on the flash interface. June 2011 Altera Corporation 1–21 Volume 2: Configuration Handbook ...

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... OE, it waits for the nSTATUS-OE line to go high before starting the FPGA configuration process. This pin contains a programmable internal weak pull-up resistor of 6K that can be disabled/enabled in the Quartus II software through the Disable nCS and OE pull option. Pin Description - ups on configuration device June 2011 Altera Corporation ...

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... OE# (1) Input WE# June 2011 Altera Corporation Description These pins are the address input to the flash memory for read and write operations. The addresses are internally latched during a write cycle. When the external flash interface is not used, leave these pins floating (with a few exceptions (1)) ...

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... Connect these pins on the board to select the page specified in the Quartus II software when generating the enhanced configuration device POF. PGM[2] is the MSB. The default selection is page 0; PGM[2..0]=000. These pins must not be left floating. Pin Description of the Intel flash die CCQ without using any CC white paper. June 2011 Altera Corporation ...

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... FPGA detects a CRC error or if the FPGA’s nCONFIG input pin is asserted ■ The controller detects a configuration error and asserts OE to begin re-configuration of the Altera FPGA (for example, when CONF_DONE stays low after all configuration data has been transmitted) Power Sequencing Altera requires that you power-up the FPGA's V configuration device's POR expires ...

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... JTAG INIT_CONF instruction (Table Volume 2: Configuration Handbook Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet chapter and the Software Settings 1–11). Programming and Configuration File Support Altera Enhanced section in volume 2 of the June 2011 Altera Corporation ...

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... Enhanced configuration device instruction register length is 10 and boundary scan length is 174. f For more information about the enhanced configuration device JTAG support, refer to the BSDL files provided at the Altera website. Enhanced configuration devices can also be programmed by third-party flash programmers or on-board processors using the external flash interface. Programming files ( ...

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... You can also program the enhanced configuration devices using the Quartus II software, the Altera Programming Unit (APU), and the appropriate configuration device programming adapter. with each enhanced configuration device. Table 1–12. Programming Adapters Device EPC16 EPC8 EPC4 IEEE Std. 1149.1 (JTAG) Boundary-Scan The enhanced configuration device provides JTAG BST circuitry that complies with the IEEE Std ...

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... For more information about the flash memory (external flash interface) timing, refer to the appropriate flash data sheet on the Altera website at www.altera.com. ■ For Micron flash-based EPC4, refer to the Micron MT28F400B3 Data Sheet Flash Memory Used in EPC4 Devices at ■ ...

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... MHz 10 — — — — — — ns — — — — 100 120 ms June 2011 Altera Corporation ...

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... Low-level output voltage TTL V OL Low-level output voltage CMOS I Input leakage current I I Tri-state output off-state current OZ June 2011 Altera Corporation Table 1–19 provide information about absolute maximum ratings, Condition With respect to ground With respect to ground — — — No bias Under bias ...

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... I V supply current CCW CCW Note to Table 1–18: (1) For V supply current information, refer to the appropriate flash memory data sheet at www.altera.com. CCW Table 1–19. Enhanced Configuration Device Capacitance Symbol Parameter CIN Input pin capacitance COUT Output pin capacitance Package The EPC16 enhanced configuration device is available in both the 88-pin UFBGA package and the 100-pin PQFP package ...

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... Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Package Figure 1–8 shows the PCB routing for the 88-pin UFBGA package. The Gerber file for this layout is on the Altera website. Figure 1–8. PCB Routing for 88-Pin UFBGA Package NC VCC ...

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... Package Layout Recommendation Sharp flash-based EPC16 and EPC8 enhanced configuration devices in the 100-pin PQFP packages have different package dimensions than other Altera 100-pin PQFP devices (including the Micron flash-based EPC4, Intel flash-based EPC16, EPC8 and EPC4). Figure 1–9 configuration devices that allows for vertical migration between all devices. These footprint dimensions are based on vendor-supplied package outline diagrams. Figure 1– ...

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... April 2007 2.3 October 2005 2.2 July 2004 2.0 September 2003 1.0 June 2011 Altera Corporation Altera Configuration Devices Pin-Out Changes Updated Table 1–3 and Table 1–16. Added Table 1–1 and Table 1–2. ■ Updated Table 1–17 and Table 1–18. ...

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... Volume 2: Configuration Handbook Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Document Revision History June 2011 Altera Corporation ...