AT25DL081-MHN-T Adesto Technologies, AT25DL081-MHN-T Datasheet - Page 9

• Manufacturer Part Number: AT25DL081-MHN-T
• Description: Flash 8M 1.65-1.95V 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DL081-MHN-T

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 8 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 1.95 V
• Supply Voltage - Min: 1.65 V
• Maximum Operating Current: 20 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UDFN-8

7.
7.1
Figure 7-1. Read Array – 1Bh Opcode
SCK
CS
SO
SI
Read Commands
Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address has been specified. The device incorporates an internal
address counter that automatically increments on every clock cycle.
Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each opcode depends on the
maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock
frequency up to the maximum specified by f
to the maximum specified by f
any clock frequency up to the maximum specified by f
f
To perform the Read Array operation, the CS pin must first be asserted and then the appropriate opcode (1Bh, 0Bh, or
03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in
to specify the location of the first byte to read within the memory array. Following the three address bytes, additional
dummy bytes may need to be clocked into the device, depending on which opcode is used for the Read Array operation.
If the 1Bh opcode is used, then two dummy bytes must be clocked into the device after the three address bytes. If the
0Bh opcode is used, then a single dummy byte must be clocked in after the address bytes.
After the three address bytes (and any dummy bytes) have been clocked in, additional clock cycles will result in data
being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte (FFFFFh) of the
memory array has been read, the device will continue reading from the beginning of the array (000000h). No delays will
be incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can
be deasserted at any time and does not require that a full byte of data be read.
CLK
should be reserved for systems employing the RapidS protocol.
High-impedance
MSB
0
0
0
1
0
2
Opcode
1
3
1
4
0
5
1
6
1
7
MSB
A
8
A
RDLF
9
A
10 11
Address Bits A23-A0
. The 1Bh opcode allows the highest read performance possible and can be used at
A
A
12
A
CLK
A
29 30
, and the 03h opcode can be used for lower frequency read operations up
A
A
31 32
MSB
X
MAX
X
33
X
; however, use of the 1Bh opcode at clock frequencies above
34
Don't Care
X
35
X
36
X
37 38
X
X
39
MSB
X
40
X
41
X
42 43
Don't Care
X
X
44
AT25DL081 [DATASHEET]
X
45
X
46
X
47 48
MSB
D
D
49
D
Data Byte 1
50 51
8732E–DFLASH–1/2013
D
D
52
D
53
D
54
D
55 56
MSB
D
D
9