AT45DB161E-CCUD-T Adesto Technologies, AT45DB161E-CCUD-T Datasheet
AT45DB161E-CCUD-T
Specifications of AT45DB161E-CCUD-T
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AT45DB161E-CCUD-T Summary of contents
Page 1
... Complies with full industrial temperature range Green (Pb/Halide-free/RoHS compliant) packaging options 8-lead SOIC (0.150" wide and 0.208" wide) 8-pad Ultra-thin DFN ( 0.6mm) 9-ball Ultra-thin UBGA ( 0.6mm) AT45DB161E SPI Serial Flash Memory DATASHEET 8782D–DFLASH–11/2012 ...
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... RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of memory are organized as 4,096 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB161E also contains two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed ...
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... CC voltages may produce spurious results and should not be attempted. Asserted State Low — — — Low Low — — Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 Type Input Input Input Output Input Input Power Ground 3 ...
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... Block Diagram Figure 2-1. Block Diagram WP Page (512/528 bytes) Buffer 1 (512/528 bytes) SCK CS RESET V CC GND Flash Memory Array Buffer 2 (512/528 bytes) I/O Interface SI Adesto AT45DB161E [DATASHEET 8782D–DFLASH–11/2012 ...
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... Memory Array To provide optimal flexibility, the AT45DB161E memory array is divided into three levels of granularity comprising of sectors, blocks, and pages. Figure 3-1, Memory Architecture Diagram the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at the byte level (a variable number of bytes) ...
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... denotes the nine address bits required to designate a byte address within a page. Therefore, when using the binary page size, a total of 21 address bits are used. through Table 15-4 on page 41. A valid instruction starts with the falling Adesto AT45DB161E [DATASHEET] 6 8782D–DFLASH–11/2012 ...
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... The Continuous Array CAR1 . To perform a Continuous Array Read using the standard DataFlash CAR1 Adesto AT45DB161E [DATASHEET] Section 25., Detailed Bit-level 7 8782D–DFLASH–11/2012 ...
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... The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page specification. The Continuous Array CAR1 specification. The Continuous Array CAR1 specification. The Continuous Array CAR2 . To perform a Continuous Array Read using the standard CAR3 Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 8 ...
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... A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). specification. The Continuous Array CAR3 specification. The Main Memory Page SCK while the D1h and D3h opcode can be used for lower frequency CAR1 . CAR2 Adesto AT45DB161E [DATASHEET] 9 8782D–DFLASH–11/2012 ...
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... Buffer 2 must be clocked into the device followed by three address bytes comprised of three dummy bits, 12 page address bits (A20 - A9) that specify the page in the main memory to be written, and nine dummy bits. Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 ...
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... BFA0) that selects the first byte in the buffer to be written. After all address bytes are clocked in, the device will take data from the input pin (SI) and store it in Buffer 1. Any number of bytes (1 to 512) can be entered. If the end of the . During this time, the RDY/BUSY bit in the P . During this time, the EP Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 11 ...
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... The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error arises, it will be indicated by the EPE bit in the Status Register. time depending on the number of bytes being BP . During this time, the PE . During this time, the RDY/BUSY bit in BE Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 12 ...
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... • • • • • • • • • • • • Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 Block • • • 508 509 510 511 13 ...
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... X X • • • • • • • • • • • • Byte 2 Byte 3 Byte 4 94h 80h 9Ah Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 • • • ...
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... One of the Program Suspend SUSP Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 15 ...
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... Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Allowed Adesto AT45DB161E [DATASHEET] Operation During Erase Suspend (ES) Allowed Allowed Allowed Allowed Allowed Not Allowed Not Allowed Allowed Allowed Not Allowed Not Allowed ...
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... RDY/BUSY bit or the appropriate PS1, PS2 bit in the Status Register to determine if the previously suspended program or erase operation has resumed. RES time before issuing the Program/Erase Suspend command must RES Adesto AT45DB161E [DATASHEET] . The PS1 bit, PS2 bit bit in 17 8782D–DFLASH–11/2012 ...
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... After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to disable the sector protection. Table 7-2. Disable Sector Protection Command Command Disable Sector Protection Byte 1 3Dh 2Ah 7Fh A9h Byte 1 3Dh Byte 2 Byte 3 Byte 4 2Ah 7Fh A9h Byte 2 Byte 3 Byte 4 2Ah 7Fh 9Ah Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 18 ...
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... Not Issued Yet — Issue Command Issue Command time. When the WPE 3 Sector Sector Protection Protection Status Register X Disabled Read/Write Disabled Read/Write — Enabled Read/Write X Enabled Read Enabled Read/Write Disabled Read/Write — Enabled Read/Write Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 19 ...
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... Table 7-5 Bit 7:6 Bit 5:4 Bit 3:2 Sector 0a Sector 0b (Page 0-7) (Page 8-255) N Byte 1 Byte 2 Byte 3 3Dh 2Ah 7Fh Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 Table 7 FFh 00h Bit 1:0 Data N/A Value XX 0xh XX Cxh XX 3xh XX Fxh Byte 4 CFh 20 ...
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... Figure 7-5. Program Sector Protection Register CS SI 3Dh Each transition represents eight bits 2Ah 7Fh CFh Byte 1 3Dh Data Byte 2Ah 7Fh FCh n . During this time, P Byte 2 Byte 3 Byte 4 2Ah 7Fh FCh Data Byte Data Byte Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 21 ...
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... Byte 1 32h Data n Byte 2 Byte 3 Byte 4 XXh XXh XXh Data Data Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 22 ...
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... Table 8-2 . During this time, the RDY/BUSY bit in the Status P Byte 1 3Dh Address 2Ah 7Fh 30h byte details the format the Sector Lockdown Register. Byte 2 Byte 3 Byte 4 2Ah 7Fh 30h Address Address byte byte Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 23 ...
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... N/A N Byte 2 Byte 3 Byte 4 XXh XXh Data Data addition, the SLE LOCK Byte 2 Byte 3 Byte 4 55h AAh Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 Data Value 00h C0h 30h F0h XXh 40h 24 ...
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... AAh 40h Security Register Byte Number 1 · · · · · · Factory Programmed by Adesto , during which time the RDY/BUSY bit in P Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 127 25 ...
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... Deasserting the CS pin will terminate the Read Security Register operation and put the SO pin into a high-impedance state. Figure 8-5. Read Security Register CS SI 77h SO Each transition represents eight bits Data 00h 00h 00h Data n Data Data Data Data Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 26 ...
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... CS pin, the part will first transfer data from the page in main memory to a buffer and then ), the RDY/BUSY bit in the Status Register can be read to XFR ), the RDY/BUSY bit in the Status Register will indicate that COMP Adesto AT45DB161E [DATASHEET] 27 8782D–DFLASH–11/2012 ...
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... Sector protection is disabled Sector protection is enabled. 0 Device is configured for standard DataFlash page size (528 bytes Device is configured for “power of 2” binary page size (512 bytes). Figure 26-1 on page 61 is recommended. Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 28 ...
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... DENSITY Bits The device density is indicated using the DENSITY bits. For the AT45DB161E, the four bit binary value is 1011. The decimal value of these four binary bits does not actually equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices. The DENSITY bits are not the same as the density code indicated in the JEDEC Device ID information ...
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... Buffer 1 was being used, and any command attempts that would modify the contents of Buffer 1 will be ignored. 9.4.10 The ES bit The ES bit indicates whether or not an erase has been suspended. If the ES bit is a Logic 1, then an erase operation (page, block, sector, or chip) has been suspended. Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 30 ...
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... Deep Power-Down mode. Figure 10-1. Deep Power-Down SCK Opcode MSB High-impedance SO Active Current I CC Standby Mode Current t EDPD Deep Power-Down Mode Current . EDPD Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 31 ...
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... Deep Power-Down mode. Figure 10-2. Resume from Deep Power-Down SCK Opcode MSB High-impedance SO Active Current I CC Deep Power-Down Mode Current t RDPD Standby Mode Current Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 32 ...
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... Ultra-Deep Power-Down mode. Figure 10-3. Ultra-Deep Power-Down SCK Opcode MSB High-impedance SO Active Current I CC Standby Mode Current t EUDPD Ultra-Deep Power-Down Mode Current EUDPD Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 . 33 ...
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... Figure 10-4. Exit Ultra-Deep Power-Down CS t CSLU t XUDPD High-impedance SO Active Current I CC Ultra-Deep Power-Down Mode Current time has elapsed in an attempt to start a new XUDPD Standby Mode Current Adesto AT45DB161E [DATASHEET] 34 8782D–DFLASH–11/2012 ...
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... The memory array of DataFlash devices is actually larger than other Serial Flash devices in that extra user-accessible bytes are provided in each page of the memory array. For the AT45DB161E, there are an extra 16 bytes of memory in each page for a total of an extra 64KB (512-Kbits) of user-accessible memory. Therefore, the device density is actually 16 ...
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... Hex Valu e Details 1Fh JEDEC code: 0001 1111 (1Fh for Adesto) Family code: 001 (AT45Dxxx Family) 26h Density code: 00110 (16-Mbit) Sub code: 000 (Standard Series) 00h Product variant:00000 Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 36 ...
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... Device ID Device ID EDI Byte 1 Byte 2 String Length Adesto AT45DB161E [DATASHEET] Details RFU: Reserved for Future Use Device revision:00000 (Initial Version 00h EDI Data Byte 1 37 8782D–DFLASH–11/2012 ...
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... Table 13-1. Software Reset Command Software Reset Figure 13-1. Software Reset CS SI F0h Each transition represents eight bits 00h 00h 00h SWRST Byte 1 Byte 2 Byte 3 Byte 4 F0h 00h 00h Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 . Since 00h 38 ...
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... Most of the commands in Group B can be suspended and resumed, except the Buffer Transfer, Buffer Compare, and Auto Page Rewrite operations Group B command is suspended, all of the Group A commands can be executed. See Table 6-4 to determine which of the Group B, Group C, and Group D commands are allowed. Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 39 ...
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... Program/Erase Suspend Program/Erase Resume Opcode D2h 01h 03h 0Bh 1Bh E8h D1h D3h D4h D6h Opcode 84h 87h 83h 86h 88h 89h 82h 85h 02h 81h 50h 7Ch C7h + 94h + 80h + 9Ah B0h D0h Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 40 ...
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... Opcode 53h 55h 60h 61h 58h 59h B9h ABh 79h D7h 9Fh 3Dh + 2Ah + 80h + A6h 3Dh + 2Ah + 80h + A7h F0h + 00h + 00h + 00h Opcode 54H 56H 52H 68H 57H Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 41 ...
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... N/A Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 Additional Dummy Bytes N/A N/A N N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N N/A 42 ...
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... N/A Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 Additional Dummy Bytes N/A N/A N N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N N/A 43 ...
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... VCSL level and an internal device delay has elapsed. This delay will CC Min 70 1.5 Read Operation Permitted t VCSL t Program/Erase Operations Permitted PUW Adesto AT45DB161E [DATASHEET] ). During this time, POR Max Units μ 2.2 V Time 44 8782D–DFLASH–11/2012 ...
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... The supply voltage regulator needs to be able to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erasing can lead to improper operation and possible data corruption. Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 45 ...
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... Maximum Ratings” are intended to accommodate short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any extended period of time. + 0.6V CC AT45DB161E 2.3V Version Industrial -40C to 85C 2.3V to 3.6V Adesto AT45DB161E [DATASHEET] AT45DB161E 2.5V Version -40C to 85C 2.5V to 3.6V 46 8782D–DFLASH–11/2012 ...
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... V = 3.6V OUT 85MHz 0mA 3.6V OUT 3. 3.6V CC All inputs at CMOS levels All inputs at CMOS levels 1.6mA 2. -100μ Adesto AT45DB161E [DATASHEET] Min Typ Max Units 0.4 1 μ μ μ 6 7 ...
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... Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 Units MHz MHz MHz MHz ns ns V/ns V/ μs μs μs μs ns μs μs μs μ ...
Page 49
... AC CC Driving Levels 0. < 2ns (10 20. Output Test Load Device Under Test 30pF Program Erase Program Erase Measurement CC Level Adesto AT45DB161E [DATASHEET] Min Typ Max Units μ 100 ms 1.4 3 μs ...
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... Slave clocks out first bit of BYTE-SO G. Master clocks in first bit of BYTE-SO H. Slave clocks out second bit of BYTE-SO I. Master clocks in last bit of BYTE- LSB BYTE-MOSI MSB BYTE-SO Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 1 LSB 50 ...
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... Page Address Dummy Bits (PA11 - PA0) 8-bits 8-bits Byte/Buffer Address (A8 - A0/BFA8 - BFA0) 8-bits 8-bits Byte/Buffer Address (BA9 - BA0/BFA9 - BFA0) Adesto AT45DB161E [DATASHEET] LSB LSB 51 8782D–DFLASH–11/2012 ...
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... These timing waveforms are valid over the CSH Valid Out CSH t HO Valid Out t H Valid In 22-4. Waveform 1 shows the SCK signal being DIS High-impedance DIS High-impedance Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 52 ...
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... Valid In Figure 22-4. Waveform 4 = RapidS Mode CSS WL SCK t V High Valid CSH Valid Out CSH t HO Valid Out t H Adesto AT45DB161E [DATASHEET DIS High-impedance DIS High-impedance 53 8782D–DFLASH–11/2012 ...
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... Dummy Bits + BFA8-BFA0 X X···X, BFA9-8 BFA7-0 n Binary Page Size A20- Dummy Bits PA11-6 PA5-0, XX XXXX 1st byte read n+1 = 2nd byte read Adesto AT45DB161E [DATASHEET] Buffer 2 To Main Memory Page Program Buffer 2 Write Last Byte 8782D–DFLASH–11/2012 54 ...
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... Flash Memory Array Buffer 2 (512/528 bytes) Main Memory Page Read I/O Interface SO Address for Binary Page Size A20-A16 A15-A8 A7-A0 CMD PA11-6 PA5-0, BA9-8 BA7-0 Main Memory Page To Buffer 2 Buffer 2 Read Dummy Bytes Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 55 ...
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... Binary Page Size A20- Dummy Bits PA11-6 PA5-0, XX XXXX XX Address for Binary Page Size A20-A16 A15-A8 A7-A0 X X... X, BFA9-8 BFA7 Dummy Byte (opcodes D1H and D3H) 1 Dummy Byte (opcodes D4H and D6H) Adesto AT45DB161E [DATASHEET 8782D–DFLASH–11/2012 ...
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... Dummy Bits Data Byte MSB Data Byte MSB Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 MSB Bit 0 of Page n MSB 57 ...
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... MSB Data Byte MSB Adesto AT45DB161E [DATASHEET Data Byte MSB MSB ...
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... D D MSB Dummy Bits MSB Data Byte MSB Adesto AT45DB161E [DATASHEET MSB MSB ...
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... MSB MSB 26h 00h Device ID Device ID Byte 1 Byte 2 String Length Adesto AT45DB161E [DATASHEET MSB 01h 00h EDI EDI Data Byte 1 t REC t CSS t RST High Impedance 8782D–DFLASH–11/2012 60 ...
Page 61
... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array START Provide Address through Buffer (82h, 85h) END and Data Buffer Write (84h, 87h) Buffer To Main Memory Page Program (83h, 86h) Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 61 ...
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... If planning to modify multiple to Buffer Transfer bytes currently stored within (53h, 55h) a page of the Flash array Buffer Write (84h, 87h) Buffer to Main Memory Page Program (83h, 86h) (2) Auto Page Rewrite (58h, 59h) Increment Page (2) Address Pointer END Adesto AT45DB161E [DATASHEET] 62 8782D–DFLASH–11/2012 ...
Page 63
... U = Green, Matte alloy, Industrial temperature range (–40°C to +85°C) Package Option SS = 8-lead, 0.150” wide SOIC S = 8-lead, 0.208” wide SOIC M = 8-pad 0.6mm UDFN CC = 9-ball (1mm pitch) UBGA Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 63 ...
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... Ordering Code (1) AT45DB161E-SSHD-B (1) AT45DB161E-SSHD-T (1)(2) AT45DB161E-SHD-B (1)(2) AT45DB161E-SHD-T (1) AT45DB161E-MHD-Y (1) AT45DB161E-MHD-T (1) AT45DB161E-CCUD-T (1) AT45DB161E-SSHF-B (1) AT45DB161E-SSHF-T (1) AT45DB161E-MHF-Y (1) AT45DB161E-MHF-T Notes: 1. The shipping carrier suffix is not marked on the device. 2. Not recommended for new design. Use the 8S1 package option. 8S1 8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8S2 8-lead 0.208" ...
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... Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN) Package Lead Finish Operating Voltage 8S1 8S2 NiPdAu 2.5V to 3.6V 8MA1 8S1 NiPdAu 2.3V to 3.6V 8MA1 Package Type Adesto AT45DB161E [DATASHEET] f Device Grade SCK Industrial 85MHz (-40C to 85C) Industrial 85MHz (-40C to 85C) 65 8782D–DFLASH–11/2012 ...
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... Small Outline (JEDEC SOIC Ø END VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 Ø Ø 0° – 8° GPC DRAWING NO. REV. SWB 8S1 Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 6/22/ ...
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... TOP VIEW TOP VIEW SIDE VIEW SIDE VIEW TITLE 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) Adesto AT45DB161E [DATASHEET END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM ...
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... Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) C SIDE VIEW y A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM 0.45 0.55 0.60 A1 0.00 0.02 0.05 b 0.35 0.40 0.48 C 0.152 REF D 4.90 5.00 5.10 D2 3.80 4.00 4.20 E 5.90 6.00 6.10 E2 3.20 3.40 3.60 e 1.27 L 0.50 0.60 0.75 y 0.00 – 0.08 K 0.20 – – GPC DRAWING NO. YFG 8MA1 Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 4/15/08 REV ...
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... ORIGINAL/RAW BALL 0. 0.05 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – 0.53 0.60 A1 0.12 – 0.38 REF D 5.90 6.00 6.10 D1 2.00 BSC E 5.90 6.00 6.10 E1 2.00 BSC b 0.35 0.40 0.45 Note 1 e 1.00 BSC DRAWING NO. GPC 9CC1 CAA Adesto AT45DB161E [DATASHEET] 8782D–DFLASH–11/2012 6/30/09 REV ...
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... Update to Adesto logos. Update preliminary to complete datasheet status. Correct pinout drawings to state top view. 8782C 07/2012 Increase t Update ordering detail to add 2B equals factory set 512 byte binary page size option. maximum from 70μs to 120μs. XUDPD Adesto AT45DB161E [DATASHEET] 70 8782D–DFLASH–11/2012 ...
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... CC0 CC1 to I – 33MHZ, increase maximum from 17mA to 19mA; CC1 CC2 to I – remove erase operation, decrease typical from 15mA to 12mA and CC2 CC3 , and t . SECP SECUP Adesto AT45DB161E [DATASHEET] = 3.6V with typical 7.5mA and 71 8782D–DFLASH–11/2012 ...
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... Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...